公开(公告)号：US09343329B2

公开(公告)日：2016-05-17

申请号：US14620766

申请日：2015-02-12

Applicant: IMEC VZW

Inventor： Alexey Milenin ,  Liesbeth Witters

IPC: H01L21/3205 ,  H01L21/311 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract translation: 一种用于在半导体结构的含锗接触区域上形成接触的方法，所述方法包括以下步骤：提供所述半导体结构，包括：（i）含Ge接触区域，（ii）任选的SiO 2层涂层 所述含Ge接触区域，（iii）涂覆所述SiO 2层（如果存在）或所述含Ge接触区域的Si 3 N 4层; 通过电感耦合等离子体选择性地蚀刻Si 3 N 4层，从而暴露下面的SiO 2层（如果存在）或含Ge接触区域; 选择性地蚀刻SiO 2层（如果存在），从而暴露SiGe：B接触区域; 以及在所述含Ge接触区域上产生所述接触。

公开(公告)号：US20150228502A1

公开(公告)日：2015-08-13

申请号：US14620766

申请日：2015-02-12

Applicant: IMEC VZW

Inventor： Alexey Milenin ,  Liesbeth Witters

IPC: H01L21/3205 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

Abstract translation: 一种用于在半导体结构的含锗接触区域上形成接触的方法，所述方法包括以下步骤：提供所述半导体结构，包括：（i）含Ge接触区域，（ii）任选的SiO 2层涂层 所述含Ge接触区域，（iii）涂覆所述SiO 2层（如果存在）或所述含Ge接触区域的Si 3 N 4层; 通过电感耦合等离子体选择性地蚀刻Si 3 N 4层，从而暴露下面的SiO 2层（如果存在）或含Ge接触区域; 选择性地蚀刻SiO 2层（如果存在），从而暴露SiGe：B接触区域; 以及在所述含Ge接触区域上产生所述接触。

公开(公告)号：US20210375668A1

公开(公告)日：2021-12-02

申请号：US17329556

申请日：2021-05-25

Applicant: IMEC VZW

Inventor： Didit Yudistira ,  Alexey Milenin

IPC: H01L21/762 ,  H01L21/306 ,  H01L21/3065 ,  H01L23/00

Abstract: A Silicon on Insulator (SOI) structure and a method for creating an undercut (UCUT) in an SOI structure, in particular, for a 300 mm SOI platform, is provided. In particular, the method includes fabricating one or more cavities in a silicon substrate underneath an insulator layer of the SOI structure by performing a first dry etch of the silicon substrate to create the one or more cavities, performing a first wet etch of the silicon substrate to expand the one or more cavities, performing a second dry etch of the silicon substrate to further expand the one or more cavities and to break silicon facets created by the first wet etch, and performing a second wet etch to further expand the one or more cavities.