公开(公告)号：US20150097187A1

公开(公告)日：2015-04-09

申请号：US14508906

申请日：2014-10-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Bogdan GOVOREANU ,  Christoph ADELMANN ,  Leqi ZHANG ,  Malgorzata JURCZAK

IPC: H01L29/861 ,  H01L29/45 ,  H01L29/16

CPC classification number: H01L29/861 ,  H01L27/2418 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/456 ,  H01L29/88 ,  H01L45/00

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及用于具有电阻开关元件，特别是电阻随机存取存储器（RRAM）器件的存储器件的选择器器件。 一方面，选择器装置包括第一阻挡结构，其包括第一金属和第一半导体或第一低带隙电介质材料，以及包括第二金属和第二半导体或第二低带隙电介质材料的第二阻挡结构。 选择器装置还包括插入在第一半导体或第一低带隙电介质材料和第二半导体或第二低带隙电介质材料之间的绝缘体。 层叠第一阻挡结构，绝缘体和第二阻挡结构以形成金属/半导体或低带隙电介质/绝缘体/半导体或低带隙电介质/金属结构。

公开(公告)号：US20170179373A1

公开(公告)日：2017-06-22

申请号：US15387350

申请日：2016-12-21

Applicant: IMEC VZW

Inventor： Johan Swerts ,  Mauricio MANFRINI ,  Christoph ADELMANN

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/18 ,  H03K19/23

Abstract: The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.