Gate Spacer Patterning
    3.
    发明申请

    公开(公告)号:US20220084822A1

    公开(公告)日:2022-03-17

    申请号:US17371936

    申请日:2021-07-09

    Applicant: IMEC VZW

    Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.

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