公开(公告)号：US20170141199A1

公开(公告)日：2017-05-18

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L29/08 ,  H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/41791 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US20150130062A1

公开(公告)日：2015-05-14

申请号：US14400769

申请日：2013-05-14

Applicant: IMEC VZW

Inventor： Laure Elisa Carbonell ,  Antony Premkumar Peter ,  Marc Schaekers ,  Sven Van Elshocht ,  Zsolt Tokei

IPC: H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

Abstract translation: 用于形成互连结构的方法，包括以下步骤：在基底上的电介质材料中形成凹陷结构; 用选自铜，镍和钴的金属至少部分地填充所述凹陷结构; 将衬底引入CVD反应器中; 使衬底在CVD反应器中达到浸泡温度，随后通过在浸泡温度下将锗前体气体供应至CVD反应器，从而基本上将凹陷结构中的金属完全转化为锗化物，进行浸泡处理。

公开(公告)号：US11854803B2

公开(公告)日：2023-12-26

申请号：US17371936

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Pierre Morin ,  Antony Premkumar Peter

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/02636 ,  H01L21/0228 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/3212 ,  H01L21/823431 ,  H01L29/6681

Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.

公开(公告)号：US20220084822A1

公开(公告)日：2022-03-17

申请号：US17371936

申请日：2021-07-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Pierre Morin ,  Antony Premkumar Peter

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/321

Abstract: A method for protecting a gate spacer when forming a FinFET structure, the method comprising: providing a fin with at least one dummy gate crossing the fin wherein a gate hardmask is present on top of the dummy gate; providing a gate spacer such that it is covering the dummy gate and the gate hardmask; recessing the gate spacer such that at least a part of the gate hardmask is exposed; selectively growing, by means of area selective deposition, extra capping material over the exposed part of the gate hardmask.

公开(公告)号：US11075083B2

公开(公告)日：2021-07-27

申请号：US16692427

申请日：2019-11-22

Applicant: IMEC VZW

Inventor： Hiroaki Arimura ,  Antony Premkumar Peter ,  Hendrik F. W. Dekkers

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/51

Abstract: A method for forming a gate stack of a field-effect transistor includes depositing a Si capping layer on a Ge channel material (100). The method further includes depositing an oxide layer on the Si capping layer by a plasma enhanced deposition technique at a temperature less than or equal to 200° C., and a plasma power less than or equal to 100 W.

公开(公告)号：US10090393B2

公开(公告)日：2018-10-02

申请号：US15345782

申请日：2016-11-08

Applicant: IMEC VZW

Inventor： Steven Demuynck ,  Zheng Tao ,  Boon Teik Chan ,  Liesbeth Witters ,  Marc Schaekers ,  Antony Premkumar Peter ,  Silvia Armini

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor structure is provided. The method includes providing a patterned substrate comprising a semiconductor region and a dielectric region. A conformal layer of a first dielectric material is deposited directly on the patterned substrate. A layer of a sacrificial material is deposited overlying the conformal layer of the first dielectric material. The sacrificial material is patterned, whereby a part of the semiconductor region remains covered by the patterned sacrificial material. A layer of a second dielectric material is deposited on the patterned substrate, thereby completely covering the patterned sacrificial material. A recess is formed in the second dielectric material by completely removing the patterned sacrificial material. The exposed conformal layer of the first dielectric material is removed selectively to the semiconductor region.

公开(公告)号：US09997458B2

公开(公告)日：2018-06-12

申请号：US14400769

申请日：2013-05-14

Applicant: IMEC VZW

Inventor： Laure Elisa Carbonell ,  Antony Premkumar Peter ,  Marc Schaekers ,  Sven Van Elshocht ,  Zsolt Tokei

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/321 ,  H01L23/528 ,  H01L21/285

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.

公开(公告)号：US09633853B2

公开(公告)日：2017-04-25

申请号：US14957989

申请日：2015-12-03

Applicant: IMEC VZW

Inventor： Antony Premkumar Peter ,  Marc Schaekers

IPC: H01L21/24 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L29/08 ,  H01L21/02 ,  H01L21/205 ,  H01L21/285

CPC classification number: H01L21/244 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2053 ,  H01L21/24 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76886 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

公开(公告)号：US20160163648A1

公开(公告)日：2016-06-09

申请号：US14957989

申请日：2015-12-03

Applicant: IMEC VZW

Inventor： Antony Premkumar Peter ,  Marc Schaekers

IPC: H01L23/535 ,  H01L23/532 ,  H01L29/08 ,  H01L21/768

CPC classification number: H01L21/244 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2053 ,  H01L21/24 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76886 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas.

Abstract translation: 提供了一种用于形成与半导体结构的电接触的方法。 该方法包括提供半导体结构，在所述半导体结构的区域上提供金属，其中所述区域暴露半导体材料并且是接触区域的至少一部分，将所述金属转化为包含Si的或包含Ge的 合金，从而在所述区域上形成所述电接触，其中所述转化通过进行气 - 固反应进行，由此使包括所述金属的所述半导体结构经受含硅的前体气体或包含锗的前体气体。