公开(公告)号：US20230395376A1

公开(公告)日：2023-12-07

申请号：US18324752

申请日：2023-05-26

Applicant: IMEC vzw

Inventor： Bertrand Parvais ,  Sachin Yadav ,  Ming Zhao ,  Pieter Cardinael

IPC: H01L21/02 ,  H01L21/322 ,  H01L29/20

CPC classification number: H01L21/0254 ,  H01L21/02181 ,  H01L21/3223 ,  H01L29/2003 ,  H01L21/02381 ,  H01L21/02164 ,  H01L21/0245 ,  H01L21/02532

Abstract: In one aspect, a substrate includes a base substrate, a dielectric layer directly on the base substrate, a trap-rich layer directly on the dielectric layer, and a crystalline semiconductor layer directly on the trap-rich layer. The dielectric layer may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate can be suitable to epitaxially grow on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor. One application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable to process in and/or on the layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, can enable the neutralization of a parasitic surface conductive (PSC) layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer. The disclosed technology is equally related to methods of producing the substrate of the disclosed technology.

公开(公告)号：US20230010039A1

公开(公告)日：2023-01-12

申请号：US17859294

申请日：2022-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Martin Heilmann ,  Ming Zhao ,  Nadine Collaert ,  Bertrand Parvais ,  Sachin Yadav

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/02 ,  C30B29/06 ,  C30B25/18 ,  C30B29/40 ,  C23C16/30 ,  C23C16/02

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

公开(公告)号：US20200004285A1

公开(公告)日：2020-01-02

申请号：US16452143

申请日：2019-06-25

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Bertrand Parvais

IPC: G05F1/595

Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).

公开(公告)号：US11205716B2

公开(公告)日：2021-12-21

申请号：US16662671

申请日：2019-10-24

Applicant: IMEC VZW

Inventor： Veeresh Vidyadhar Deshpande ,  Bertrand Parvais

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/267 ,  H01L29/66

Abstract: A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.

公开(公告)号：US10712760B2

公开(公告)日：2020-07-14

申请号：US16452143

申请日：2019-06-25

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Bertrand Parvais

IPC: G05F1/595 ,  H01L29/76

Abstract: Example embodiments relate to low-temperature voltage references using Coulomb blockade mechanisms. One embodiment includes a method of generating a reference voltage. The method includes providing a first single-electron transistor (SET) and a second SET connected in series. The method also includes biasing the first SET and the second SET using a same biasing current (Ib). Further, the method includes operating the first SET at a slope of a first Coulomb peak and the second SET at a slope of a second Coulomb peak. The slope of the first Coulomb peak and the second Coulomb peak are of the same slope type selected from a rising slope, a peak maximum, and a falling slope. The second Coulomb peak is different from the first Coulomb peak. Additionally, the method includes generating the reference voltage (Vref) based on a difference between gate-to-source voltages of the first SET (Vgs1) and the second SET (Vgs2).