公开(公告)号：US12100727B2

公开(公告)日：2024-09-24

申请号：US17418148

申请日：2019-12-23

申请人： Soitec

发明人： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC分类号： H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

CPC分类号： H01L27/14683 ,  H01L21/26506 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76254 ,  H01L27/1463 ,  H01L31/1892

摘要： A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

公开(公告)号：US20230395376A1

公开(公告)日：2023-12-07

申请号：US18324752

申请日：2023-05-26

申请人： IMEC vzw

发明人： Bertrand Parvais ,  Sachin Yadav ,  Ming Zhao ,  Pieter Cardinael

IPC分类号： H01L21/02 ,  H01L21/322 ,  H01L29/20

CPC分类号： H01L21/0254 ,  H01L21/02181 ,  H01L21/3223 ,  H01L29/2003 ,  H01L21/02381 ,  H01L21/02164 ,  H01L21/0245 ,  H01L21/02532

摘要： In one aspect, a substrate includes a base substrate, a dielectric layer directly on the base substrate, a trap-rich layer directly on the dielectric layer, and a crystalline semiconductor layer directly on the trap-rich layer. The dielectric layer may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate can be suitable to epitaxially grow on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor. One application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable to process in and/or on the layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, can enable the neutralization of a parasitic surface conductive (PSC) layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer. The disclosed technology is equally related to methods of producing the substrate of the disclosed technology.

公开(公告)号：US09708179B2

公开(公告)日：2017-07-18

申请号：US14967663

申请日：2015-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yuan-Chih Hsieh ,  Li-Cheng Chu ,  Hung-Hua Lin ,  Chih-Jen Chan ,  Lan-Lin Chao

IPC分类号： H01L23/12 ,  B81B7/00 ,  B81C1/00 ,  H01L23/26 ,  H01L21/322

CPC分类号： B81B7/0038 ,  B81B7/0025 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0315 ,  B81C1/00285 ,  B81C2203/0118 ,  H01L21/3223 ,  H01L23/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.

公开(公告)号：US09511998B2

公开(公告)日：2016-12-06

申请号：US14207752

申请日：2014-03-13

申请人： Robert Bosch GmbH

发明人： Ashwin Samarao ,  Gary O'Brien ,  Ando Feyh ,  Gary Yama ,  Andrew Graham ,  Bongsang Kim ,  Fabian Purkl

IPC分类号： H01L21/322 ,  B81C1/00 ,  H01L23/28

CPC分类号： B81C1/00285 ,  B81C2201/0115 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/035 ,  H01L21/3223 ,  H01L21/3225 ,  H01L23/28

摘要： A microelectromechanical system (MEMS) device includes a high density getter. The high density getter includes a silicon surface area formed by porosification or by the formation of trenches within a sealed cavity of the device. The silicon surface area includes a deposition of titanium or other gettering material to reduce the amount of gas present in the sealed chamber such that a low pressure chamber is formed. The high density getter is used in bolometers and gyroscopes but is not limited to those devices.

摘要翻译： 微机电系统（MEMS）装置包括高密度吸气剂。 高密度吸气剂包括通过孔化形成的硅表面积或通过在该装置的密封腔内形成沟槽。 硅表面积包括钛或其它吸气材料的沉积物，以减少密封室中存在的气体的量，从而形成低压室。 高密度吸气剂用于测辐射仪和陀螺仪，但不限于这些设备。

公开(公告)号：US09502258B2

公开(公告)日：2016-11-22

申请号：US14581332

申请日：2014-12-23

申请人： Applied Materials, Inc.

发明人： Jun Xue ,  Ching-Mei Hsu ,  Zihui Li ,  Ludovic Godet ,  Anchuan Wang ,  Nitin K. Ingle

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/322

CPC分类号： H01L21/3065 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/3223

摘要： A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single material made from, for example, a silicon-containing material or a metal-containing material. The method includes directionally ion-implanting the patterned structure to implant the bottom of the gap without implanting substantially the walls of the gap. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that either (1) the walls are selectively etched relative to the floor of the gap, or (2) the floor is selectively etched relative to the walls of the gap. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.

摘要翻译： 描述了在图案化衬底上各向异性地干蚀刻暴露的衬底材料的方法。 图案化衬底具有由例如含硅材料或含金属材料制成的单一材料形成的间隙。 该方法包括定向离子注入图案化结构以植入间隙的底部，而基本上不插入间隙的壁。 随后，使用含氟前体形成远程等离子体以蚀刻图案化衬底，使得（1）相对于间隙的底板选择性地蚀刻壁，或者（2）相对于壁选择性地蚀刻地板 的差距。 在没有离子注入的情况下，蚀刻操作将是各向同性的，这是由于在蚀刻过程期间等离子体激发的远程特性。

公开(公告)号：US20150050798A1

公开(公告)日：2015-02-19

申请号：US14372004

申请日：2013-03-14

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yusuke Kobayashi ,  Takashi Yoshimura

IPC分类号： H01L21/322

CPC分类号： H01L21/3223 ,  H01L21/263 ,  H01L21/324 ,  H01L29/0619 ,  H01L29/32 ,  H01L29/36 ,  H01L29/402 ,  H01L29/66128 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/8611

摘要： A method for producing a semiconductor device includes providing a semiconductor substrate having a first conductivity type; implanting protons through a rear surface of the semiconductor substrate of the first conductivity type; and forming a first semiconductor region of the first conductivity type in the semiconductor substrate by performing an annealing process in an annealing furnace in a hydrogen atmosphere having a volume concentration of hydrogen that is equal to or greater than 0.5% and less than 4.65%, the first semiconductor region having a higher impurity concentration than that of the semiconductor substrate after the implantation step. The method reduces crystal defects in the generation of donors during proton implantation and improves the rate of change into a donor.

摘要翻译： 一种制造半导体器件的方法包括：提供具有第一导电类型的半导体衬底; 通过第一导电类型的半导体衬底的后表面注入质子; 以及通过在体积浓度为等于或大于0.5％且小于4.65％的氢气气氛中的退火炉中进行退火处理，在半导体衬底中形成第一导电类型的第一半导体区域， 第一半导体区域在植入步骤之后具有比半导体衬底更高的杂质浓度。 该方法在质子注入过程中减少了供体产生中的晶体缺陷，提高了供体的变化率。

公开(公告)号：US07972947B2

公开(公告)日：2011-07-05

申请号：US12119972

申请日：2008-05-13

申请人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

发明人： Luis-Felipe Giles ,  Thomas Hoffmann ,  Chris Stapelmann

IPC分类号： H01L21/425

CPC分类号： H01L21/3223 ,  H01L21/263 ,  H01L21/26506 ,  H01L29/66575 ,  H01L29/78

摘要： In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.

摘要翻译： 在衬底中制造半导体元件的方法中，将第一注入离子注入到衬底中，从而在衬底的第一部分区域中产生微腔。 此外，将非晶化离子注入到基板中，由此基板的第二部分区域至少部分非晶化，并且由此在基板中产生晶体缺陷。 此外，第二注入离子注入基片的第二部分区域。 此外，加热衬底，使得使用第二注入离子去除至少一些晶体缺陷。 此外，掺杂剂原子被注入到衬底的第二部分区域中，其中使用掺杂剂原子形成半导体元件。

公开(公告)号：US07833886B2

公开(公告)日：2010-11-16

申请号：US11748327

申请日：2007-05-14

申请人： Luis-Felipe Giles ,  Matthias Goldbach ,  Martin Bartels ,  Paul Kuepper

发明人： Luis-Felipe Giles ,  Matthias Goldbach ,  Martin Bartels ,  Paul Kuepper

IPC分类号： H01L21/04

CPC分类号： H01L21/3223 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/32 ,  H01L29/78

摘要： A method of producing a semiconductor element in a substrate includes forming a plurality of micro-cavities in a substrate, creating an amorphization of the substrate to form crystallographic defects and a doping of the substrate with doping atoms, depositing an amorphous layer on top of the substrate, and annealing the substrate, such that at least a part of the crystallographic defects is eliminated using the micro-cavities. The semiconductor element is formed using the doping atoms.

摘要翻译： 在衬底中制造半导体元件的方法包括在衬底中形成多个微腔，产生衬底的非晶化，以形成晶体缺陷和用掺杂原子掺杂衬底，将非晶层沉积在 衬底和退火衬底，使得至少一部分结晶缺陷使用微腔消除。 使用掺杂原子形成半导体元件。

公开(公告)号：US20070004109A1

公开(公告)日：2007-01-04

申请号：US11518246

申请日：2006-09-11

申请人： Mitsuhiro Ichijo ,  Taketomi Asami ,  Noriyoshi Suzuki

发明人： Mitsuhiro Ichijo ,  Taketomi Asami ,  Noriyoshi Suzuki

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/0237 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02672 ,  H01L21/02686 ,  H01L21/3221 ,  H01L21/3223 ,  H01L27/1277

摘要： A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on a semiconductor film having a crystal structure by plasma CVD from monosilane and nitrous oxide as material gas. In a step of forming a gettering site, a semiconductor film having an amorphous structure and containing a high concentration of noble gas element, specifically, 1×1020 to 1×1021/cm3, is formed by plasma CVD. The film is typically an amorphous silicon film. Then gettering is conducted.

摘要翻译： 提供一种降低元件之间的波动的技术，其中通过使用加速半导体膜的结晶的金属元素获得具有晶体结构的半导体膜，然后有效地去除残留在膜中的金属元素。 通过等离子体CVD从作为原料气体的甲硅烷和一氧化二氮形成具有晶体结构的半导体膜上的阻挡层。 在形成吸杂位点的步骤中，具有非晶结构且含有高浓度惰性气体元素的半导体膜，具体地，1×10 20至1×10 21 / cm 2， SUP> 3 ，由等离子体CVD形成。 该膜通常是非晶硅膜。 然后进行吸气。

公开(公告)号：US06821828B2

公开(公告)日：2004-11-23

申请号：US10252838

申请日：2002-09-24

申请人： Mitsuhiro Ichijo ,  Taketomi Asami ,  Noriyoshi Suzuki

发明人： Mitsuhiro Ichijo ,  Taketomi Asami ,  Noriyoshi Suzuki

IPC分类号： H01L2120

CPC分类号： H01L21/0237 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02672 ,  H01L21/02686 ,  H01L21/3221 ,  H01L21/3223 ,  H01L27/1277

摘要： A technique of reducing fluctuation between elements is provided in which a semiconductor film having a crystal structure is obtained by using a metal element that accelerates crystallization of a semiconductor film and then the metal element remaining in the film is removed effectively. A barrier layer is formed on a semiconductor film having a crystal structure by plasma CVD from monosilane and nitrous oxide as material gas. In a step of forming a gettering site, a semiconductor film having an amorphous structure and containing a high concentration of noble gas element, specifically, 1×1020 to 1×1021 /cm3, is formed by plasma CVD. The film is typically an amorphous silicon film. Then gettering is conducted.

摘要翻译： 提供一种降低元件之间的波动的技术，其中通过使用加速半导体膜的结晶的金属元素获得具有晶体结构的半导体膜，然后有效地去除残留在膜中的金属元素。 通过等离子体CVD从作为原料气体的甲硅烷和一氧化二氮形成具有晶体结构的半导体膜上的阻挡层。 在形成吸杂位置的步骤中，通过等离子体CVD形成具有非晶结构且含有高浓度惰性气体元素的半导体膜，具体地，1×10 20至1×10 21 / cm 3。 该膜通常是非晶硅膜。 然后进行吸气。