公开(公告)号：US10153341B2

公开(公告)日：2018-12-11

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  B82Y10/00

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US20210126108A1

公开(公告)日：2021-04-29

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US10593765B2

公开(公告)日：2020-03-17

申请号：US16170674

申请日：2018-10-25

Applicant: IMEC VZW

Inventor： Soon Aik Chew ,  Steven Demuynck

IPC: H01L29/51 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768

Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

公开(公告)号：US09105746B2

公开(公告)日：2015-08-11

申请号：US14521083

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

公开(公告)号：US11430876B2

公开(公告)日：2022-08-30

申请号：US17083125

申请日：2020-10-28

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Dunja Radisic ,  Steven Demuynck ,  Efrain Altamirano Sanchez ,  Soon Aik Chew

IPC: H01L29/66 ,  H01L21/768

Abstract: The disclosed technology is related to a method that includes the formation of contact vias for contacting gate electrodes and source (S) or drain (D) electrodes of nano-sized semiconductor transistors formed on a semiconductor wafer. The electrodes are mutually parallel and provided with dielectric gate and S/D plugs on top of the electrodes, and the mutually parallel electrode/plug assemblies are separated by dielectric spacers. The formation of the vias takes place by two separate self-aligned etch processes, the Vint-A etch for forming one or more vias towards one or more S/D electrodes and the Vint-G etch for forming one or more vias towards one or more gate electrodes. According to the disclosed technology, a conformal layer is deposited on the wafer after the first self-aligned etch process, wherein the conformal layer is resistant to the second self-aligned etch process. The conformal layer thereby protects the first contact via during the second self-aligned etch.

公开(公告)号：US20150357244A1

公开(公告)日：2015-12-10

申请号：US14733880

申请日：2015-06-08

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Tom Schram ,  Hendrik F.W. Dekkers ,  Soon Aik Chew

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/28

CPC classification number: H01L27/112 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/82345 ,  H01L21/823842

Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

Abstract translation: 所公开的技术通常涉及包括晶体管的半导体器件，更具体地涉及包括具有不同有效功函的栅叠层的晶体管的半导体器件，以及制造这种器件的方法。 在一个方面，制造半导体的方法包括在衬底中提供至少两个沟道区，并在衬底上提供介电层。 该方法还包括通过在电介质层中设置开口来形成多个栅极区域。 该方法还包括在开口中提供栅极电介质层，并且在每个栅极区域的栅极电介质层上提供沿着不同栅极区域具有不同厚度的势垒层叠层。

公开(公告)号：US20150111351A1

公开(公告)日：2015-04-23

申请号：US14521083

申请日：2014-10-22

Applicant: IMEC VZW

Inventor： Min-Soo Kim ,  Guillaume Boccardi ,  Soon Aik Chew ,  Naoto Horiguchi

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02126 ,  H01L21/76205 ,  H01L21/82385 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7851

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures. Further, the method includes removing an upper portion of at least two shallow trench isolation structures to expose at least a portion of the sidewalls of the fin structures within the gate trench, and forming a final gate stack in the gate trench.

Abstract translation: 一种用于制造非平面型场效应晶体管的方法，包括提供具有初始平面的前主表面的基板，并且在所述前表面上的所述基板中提供浅沟槽隔离结构，从而在所述基板中限定多个鳍结构 衬底之间的浅沟槽隔离结构。 浅沟槽隔离结构和翅片结构的顶表面邻接在共同的平坦表面上，翅片结构的侧壁被浅沟槽隔离结构完全隐藏。 该方法还包括在公共平面上的多个翅片结构的中心部分上形成虚拟栅极结构，在虚拟栅极结构周围形成介质间隔物结构，以及去除伪栅极结构，由此留下由 电介质间隔结构。 此外，该方法包括去除至少两个浅沟槽隔离结构的上部以暴露栅极沟槽内的翅片结构的侧壁的至少一部分，以及在栅极沟槽中形成最终的栅极叠层。

公开(公告)号：US20190131411A1

公开(公告)日：2019-05-02

申请号：US16170674

申请日：2018-10-25

Applicant: IMEC VZW

Inventor： Soon Aik Chew ,  Steven Demuynck

IPC: H01L29/40 ,  H01L29/51 ,  H01L21/311 ,  H01L29/66 ,  H01L29/417 ,  H01L21/3105

CPC classification number: H01L29/401 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/513 ,  H01L29/66795

Abstract: Example embodiments relate to methods for forming source/drain contacts. One embodiment includes a method for forming a source contact and a drain contact in a semiconductor structure. The method includes providing a semiconductor structure that includes a semiconductor active area having channel, source, and drain regions, a gate structure on the channel region, a gate plug on the gate structure, spacers lining side walls of the gate structure and of the gate plug, an etch stop layer covering the source and gain regions, a sacrificial material on the etch stop layer over the source and drain regions, and a masking structure that masks the source and drain regions. The method also includes forming gaps, removing the masking structure, filling the gaps, exposing the sacrificial material, removing the sacrificial material, removing the etch stop layer, and forming the source contact and the drain contact by depositing a conductive material.

公开(公告)号：US20180166534A1

公开(公告)日：2018-06-14

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02532 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US09287273B2

公开(公告)日：2016-03-15

申请号：US14733880

申请日：2015-06-08

Applicant: IMEC VZW

Inventor： Lars-Ake Ragnarsson ,  Tom Schram ,  Hendrik F. W. Dekkers ,  Soon Aik Chew

IPC: H01L21/8234 ,  H01L27/112

CPC classification number: H01L27/112 ,  H01L21/28088 ,  H01L21/28556 ,  H01L21/82345 ,  H01L21/823842

Abstract: The disclosed technology generally relates a semiconductor device comprising transistors, and more particularly to a semiconductor device comprising transistors each having a gate stack with a different effective work function, and methods of fabricating such a device. In one aspect, the method of fabricating the semiconductor comprises providing at least two channel regions in the substrate and providing a dielectric layer on the substrate. The method additionally includes forming a plurality of gate regions by providing openings in the dielectric layer. The method further includes providing a gate dielectric layer in the openings and providing on the gate dielectric layer of each of the gate regions a barrier layer stack having different thickness along the different gate regions.

Abstract translation: 所公开的技术通常涉及包括晶体管的半导体器件，更具体地涉及包括具有不同有效功函的栅叠层的晶体管的半导体器件，以及制造这种器件的方法。 在一个方面，制造半导体的方法包括在衬底中提供至少两个沟道区，并在衬底上提供介电层。 该方法还包括通过在电介质层中设置开口来形成多个栅极区域。 该方法还包括在开口中提供栅极电介质层，并且在每个栅极区域的栅极电介质层上提供沿着不同栅极区域具有不同厚度的势垒层叠层。