公开(公告)号：US10460067B2

公开(公告)日：2019-10-29

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/30 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  H01L21/762 ,  H01L27/118

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US20190229196A1

公开(公告)日：2019-07-25

申请号：US16253321

申请日：2019-01-22

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

公开(公告)号：US20190303525A9

公开(公告)日：2019-10-03

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.

公开(公告)号：US10833161B2

公开(公告)日：2020-11-10

申请号：US16253321

申请日：2019-01-22

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Julien Ryckaert ,  Juergen Boemmels ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second semiconductor structure.

公开(公告)号：US20180113975A1

公开(公告)日：2018-04-26

申请号：US15791210

申请日：2017-10-23

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Syed Muhammad Yasser Sherazi ,  Guillaume Bouche ,  Julien Ryckaert

IPC: G06F17/50 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/84 ,  H01L27/02 ,  H01L27/11 ,  H01L27/12

Abstract: The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of defining routing tracks for a standard cell semiconductor device, and to the standard cell semiconductor device fabricated using the method. In one aspect, a method of defining routing tracks in a target layer over a standard cell semiconductor device includes forming mandrels and forming a first set and a second set of spacers for defining the routing tracks. The standard cell semiconductor device includes a device layer and the routing tracks for contacting a device layer. The routing tracks include at least two pairs of off-center routing tracks, a central routing track arranged between the pairs of off-center routing tracks, and at least two edge tracks arranged on opposing sides of the at least two pairs of off-center routing tracks. A minimum distance between an off-center routing track and the central routing track next to the off-center routing track is smaller than a minimum distance between adjacent off-center routing tracks.