公开(公告)号：US20190221610A1

公开(公告)日：2019-07-18

申请号：US16234381

申请日：2018-12-27

Applicant: IMEC vzw

Inventor： Romain Delhougne ,  Davide Francesco Crotti ,  Gouri Sankar Kar ,  Luca Di Piazza ,  Ludovic Goux

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/11597

CPC classification number: H01L27/249 ,  H01L27/11597 ,  H01L27/2409 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1683

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

公开(公告)号：US20240107739A1

公开(公告)日：2024-03-28

申请号：US18472122

申请日：2023-09-21

Applicant: IMEC VZW

Inventor： Nouredine Rassoul ,  Hyungrock Oh ,  Romain Delhougne ,  Gouri Sankar Kar ,  Attilio Belmonte ,  Kaustuv Banerjee ,  Mohit Gupta

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A memory device configured as a dynamic random access memory is provided, comprising a first semiconductor device layer comprising a first bit cell and a second semiconductor device layer comprising a second DRAM bit cell. Further, at least one of a first and second interconnecting structure is provided, the first interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a write word line common to the gate terminal of the write transistors of the first and second bit cells, and the second interconnecting structure extending vertically between the first and second semiconductor device layer and being arranged to form a read word line common to a first source/drain terminal of the read transistors of the first and second bit cells.

公开(公告)号：US20240015984A1

公开(公告)日：2024-01-11

申请号：US18349046

申请日：2023-07-07

Applicant: IMEC VZW

Inventor： Mihaela Ioana Popovici ,  Jasper Bizindavyi ,  Jan Van Houdt ,  Romain Delhougne

IPC: H10B53/30 ,  H10B51/30 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B53/30 ,  H10B51/30 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure generally relates to a ferroelectric device, and more particularly to a ferroelectric device including a layer stack. According to embodiments, the ferroelectric device comprises a first electrode and a second electrode, and the layer stack arranged between the first electrode and the second electrode. The layer stack comprises a titanium oxide layer, a doped HZO layer arranged on the titanium oxide layer, and a niobium oxide layer arranged on the doped HZO layer.

公开(公告)号：US20220093861A1

公开(公告)日：2022-03-24

申请号：US17478208

申请日：2021-09-17

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW

Inventor： Michael Eugene Givens ,  Yongkook Park ,  Mathieu Caymax ,  Ali Haider ,  Romain Delhougne

IPC: H01L45/00 ,  G11C13/00

Abstract: Disclosed are methods and systems for depositing a material comprising a germanium chalcogenide. The material may be selectively deposited onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary devices in which the layers may be incorporated include memory devices.

公开(公告)号：US20220020882A1

公开(公告)日：2022-01-20

申请号：US17305797

申请日：2021-07-14

Applicant: IMEC vzw

Inventor： Nouredine Rassoul ,  Romain Delhougne ,  Attilio Belmonte ,  Gouri Sankar Kar

IPC: H01L29/786 ,  H01L29/66 ,  H01L23/00 ,  H01L29/24 ,  H01L29/10

Abstract: The disclosed technology generally relates to a structure for a field effect transistor (FET) device and a method of processing a FET device. In one aspect, the method can include providing a substrate, forming an oxygen passing layer on the substrate, and forming an oxygen blocking layer on the substrate. The oxygen blocking layer can be arranged next to the oxygen passing layer and can delimit the oxygen passing layer on two opposite sides. The method can also include forming an oxide semiconductor layer on the oxygen passing layer and the oxygen blocking layer, forming a gate structure on the oxide semiconductor layer in a region above the oxygen passing layer, and modifying a doping of the oxide semiconductor layer by introducing oxygen into the oxygen passing layer. At least a portion of the introduced oxygen can pass through the oxygen passing layer and into the oxide semiconductor layer.

公开(公告)号：US10825868B2

公开(公告)日：2020-11-03

申请号：US16234381

申请日：2018-12-27

Applicant: IMEC vzw

Inventor： Romain Delhougne ,  Davide Francesco Crotti ,  Gouri Sankar Kar ,  Luca Di Piazza ,  Ludovic Goux

IPC: H01L27/24 ,  H01L27/11597 ,  H01L45/00

Abstract: In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.