公开(公告)号：US20180358307A1

公开(公告)日：2018-12-13

申请号：US16108272

申请日：2018-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32503 ,  H01L2224/33505 ,  H01L2924/014 ,  H01L2924/3512

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

公开(公告)号：US20180233477A1

公开(公告)日：2018-08-16

申请号：US15487754

申请日：2017-04-14

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

CPC classification number: H01L24/29 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29076 ,  H01L2224/291 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8381 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material and an electronic device. The stress buffering material is disposed on the substrate and adjacent to the conductive layer. The electronic device is disposed on the intermetallic compound and the stress buffering material, and the electronic device is in contact with the intermetallic compound. The stress buffering material is adjacent to the conductive layer to have the conductive layer and the stress buffering material together serving as a stress buffer, so as to enhance the effect of stress buffering, thereby preventing a wafer from cracking due to stress.

公开(公告)号：US11114387B2

公开(公告)日：2021-09-07

申请号：US16108272

申请日：2018-08-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Fang-Jun Leu ,  Wei-Kuo Han ,  Kuo-Shu Kao

IPC: H01L23/00

Abstract: An electronic package structure is provided. The electronic packaging structure includes a substrate, a conductive layer disposed on the substrate, an intermetallic compound disposed on the conductive layer, a stress buffering material disposed on the substrate and adjacent to the conductive layer, and an electronic device disposed on the conductive layer and the stress buffering material. The intermetallic compound is disposed between the electronic device and the conductive layer, between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material. A maximum thickness of the intermetallic compound disposed between the electronic device and the stress buffering material, between the substrate and the stress buffering material, and between the conductive layer and the stress buffering material is greater than the thickness of the intermetallic compound disposed between the electronic device and the conductive layer.

公开(公告)号：US10672677B2

公开(公告)日：2020-06-02

申请号：US15979403

申请日：2018-05-14

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ,  Win-House Electronic Co., Ltd.

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Kuo-Shu Kao ,  Fang-Jun Leu ,  Hsin-Han Lin ,  Chih-Ming Tzeng ,  Hsiao-Ming Chang ,  Chih-Ming Shen

IPC: H01L23/31 ,  H01L23/36 ,  H01L23/373 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor chip, a guard ring, a gel layer, and a first lead frame. The guard ring is disposed on the semiconductor chip, and the gel layer is disposed on the guard ring. The first lead frame is electrically connected to the semiconductor chip, and the gel layer is located between the guard ring and the first lead frame.