公开(公告)号：US20240355767A1

公开(公告)日：2024-10-24

申请号：US18761675

申请日：2024-07-02

申请人： Infineon Technologies AG

发明人： Petteri Palm ,  Thorsten Scharf

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  H05K1/18 ,  H05K3/00

CPC分类号： H01L24/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L25/04 ,  H05K1/188 ,  H05K3/007 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H05K2203/0152

摘要： A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US12062588B2

公开(公告)日：2024-08-13

申请号：US17989894

申请日：2022-11-18

申请人： Amkor Technology Singapore Holding Pte. Ltd

发明人： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

CPC分类号： H01L23/3128 ,  H01L21/6835 ,  H01L23/49579 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/14 ,  H01L24/91 ,  H01L21/4839 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49586 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05026 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2224/85439 ,  H01L2924/00014 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2224/83444 ,  H01L2924/00014 ,  H01L2224/83439 ,  H01L2924/00014 ,  H01L2224/83447 ,  H01L2924/00014

摘要： A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US20230282601A1

公开(公告)日：2023-09-07

申请号：US18159973

申请日：2023-01-26

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yoshinori UEZATO ,  Masanori TAKAZAWA ,  Shoichiro SAKAI

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC分类号： H01L23/564 ,  H01L21/56 ,  H01L23/296 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/29139 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/92247

摘要： The present invention provides a joining that suppresses ion migration and also has excellent corrosion resistance, high bonding strength, and high reliability at the joining, and a semiconductor device. The present invention provides semiconductor joinings comprising: at least two semiconductor constituent members; and silver-containing bonding material layers that bond the semiconductor constituent members, in which a corrosion inhibitor coating layer is provided in contact with the silver-containing bonding material layers, and a semiconductor device including the same.

公开(公告)号：US20230187403A1

公开(公告)日：2023-06-15

申请号：US17703057

申请日：2022-03-24

申请人： HYUNDAI MOTOR COMPANY ,  KIA CORPORATION

发明人： Kyoung-Kook Hong ,  Su-Bin Kang ,  Young-Seok Kim

IPC分类号： H01L23/00 ,  H01L23/373

CPC分类号： H01L24/27 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L2224/2711 ,  H01L2224/3303 ,  H01L2224/8384 ,  H01L2224/27438 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83447 ,  H01L2924/10272

摘要： The present disclosure provides a method for manufacturing a double-sided cooling type power module including separately patterning a bonding material on a base film into two regions, positioning a semiconductor chip on the patterned bonding material, transferring the patterned bonding material to one surface of the semiconductor chip by pressurizing the semiconductor chip, positioning the bonding material of the semiconductor chip on an upper electrode layer formed on an upper substrate to be in contact with the upper electrode layer, and sintering an upper bonding layer by pressurizing and heating the semiconductor chip. According to the present disclosure, it is possible to separately dispose the bonding material on each of gate and source electrode parts on an upper portion of the chip even without protrusion to directly bond the chip and the substrate.

公开(公告)号：US20180257179A1

公开(公告)日：2018-09-13

申请号：US15897622

申请日：2018-02-15

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： HIDETOSHI KITAURA ,  AKIO FURUSAWA ,  KIYOHIRO HINE ,  KAZUKI SAKAI

IPC分类号： B23K35/26 ,  C22C13/02

CPC分类号： B23K35/262 ,  B23K35/0227 ,  B23K2101/40 ,  C22C13/02 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/05 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/83101 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83948 ,  H01L2924/10253 ,  H01L2924/01052 ,  H01L2924/01051 ,  H01L2924/01079

摘要： Provided is a solder alloy including an Sb content of 3 wt % or more and 15 wt % or less, a Te content of 0.01 wt % or more and 1.5 wt % or less, an Au content of 0.005 wt % or more and 1 wt % or less, and a remainder that is Sn.

公开(公告)号：US20180233469A1

公开(公告)日：2018-08-16

申请号：US15949632

申请日：2018-04-10

申请人： Infineon Technologies AG

发明人： Petteri Palm ,  Thorsten Scharf

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L24/19 ,  H01L24/83 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747

摘要： A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US10020282B2

公开(公告)日：2018-07-10

申请号：US14395876

申请日：2013-04-24

申请人： NISSAN MOTOR CO., LTD. ,  Sanken Electric Co., Ltd.

发明人： Satoshi Tanimoto ,  Yusuke Zushi ,  Yoshinori Murakami ,  Kohei Matsui ,  Shinji Sato ,  Yu Fukushima

IPC分类号： H01L23/00 ,  B23K37/04 ,  H05K3/34 ,  H05K13/04

CPC分类号： H01L24/83 ,  B23K37/0426 ,  H01L24/05 ,  H01L24/29 ,  H01L24/75 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/29118 ,  H01L2224/29144 ,  H01L2224/75101 ,  H01L2224/75305 ,  H01L2224/7531 ,  H01L2224/75314 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/7532 ,  H01L2224/75756 ,  H01L2224/7598 ,  H01L2224/75981 ,  H01L2224/83022 ,  H01L2224/83048 ,  H01L2224/83075 ,  H01L2224/83101 ,  H01L2224/832 ,  H01L2224/83211 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1037 ,  H01L2924/1067 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/3656 ,  H05K3/34 ,  H05K3/3431 ,  H05K13/0465 ,  H05K2203/0195 ,  H05K2203/0278 ,  H01L2924/00 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/01042 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01013 ,  H01L2224/05655 ,  H01L2224/83 ,  H01L2924/00012

摘要： In a heat insulating load jig 11 of the present invention, a solder material 14 having a melting point or a solidus temperature in a range between a thermal resistance temperature of a semiconductor chip 13 and a temperature 100° C. below the thermal resistance temperature is interposed between a circuit board 12 and the semiconductor chip 13; a heat insulating body 17 is placed on an upper side of the semiconductor chip 13 in this state; a metal weight 16 is disposed on the heat insulating body 17; and load is applied to the semiconductor chip 13 while the solder material 14 is melted and solidified.

公开(公告)号：US09991184B2

公开(公告)日：2018-06-05

申请号：US14648636

申请日：2013-05-28

申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

发明人： Kosuke Ikeda

IPC分类号： H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L23/42 ,  H01L23/051 ,  H01L23/00 ,  H01L25/07 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/055 ,  H01L23/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/373 ,  H01L21/50

CPC分类号： H01L23/3672 ,  H01L21/4817 ,  H01L21/50 ,  H01L21/565 ,  H01L23/051 ,  H01L23/055 ,  H01L23/16 ,  H01L23/3675 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49866 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/071 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/1318 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83447 ,  H01L2224/8348 ,  H01L2224/83815 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92247 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1611 ,  H01L2924/16152 ,  H01L2924/16724 ,  H01L2924/1679 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/01042 ,  H01L2924/01074

摘要： An electronic module 1 includes an electronic module 10 that includes a substrate 11 and an electronic element 12, an electronic module 20 that includes a substrate 21 arranged such that the principal surface 21a faces the principal surface 11a, an electronic element 22 electrically connected to the electronic element 12 with a connecting member 18 therebetween, and an electronic element 23 electrically connected to the electronic element 12 with a connecting member 19 therebetween passing through the substrate 21 in a thickness direction, the electronic module 20 thermally connected to the electronic module 10 by the connecting members 18 and 19, and a heat sink 30 that includes a housing part 31a therein and houses the electronic modules 10 and 20 in the housing part 31a such that the principal surface 11b is in contact with an inner wall surface of the housing part 31a.

公开(公告)号：US20180138111A1

公开(公告)日：2018-05-17

申请号：US15810733

申请日：2017-11-13

申请人： Infineon Technologies AG

发明人： Andreas Grassmann ,  Juergen Hoegerl ,  Angela Kessler ,  Ivan Nikitin

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/49568 ,  H01L21/4882 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/30181 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/83906 ,  H01L2924/014

摘要： A package comprising at least one electronic chip, a first heat removal body on which the at least one electronic chip is mounted by a first interconnection, a second heat removal body mounted on or above the at least one electronic chip by a second interconnection, and an encapsulant encapsulating at least part of the at least one electronic chip, part of the first heat removal body and part of the second heat removal body, wherein the first interconnection is configured to have another melting temperature than the second interconnection.

公开(公告)号：US09960140B2

公开(公告)日：2018-05-01

申请号：US15024682

申请日：2014-11-11

申请人： NIPPON STEEL & SUMITOMO METAL CORPORATION ,  WASEDA University

发明人： Kohei Tatsumi ,  Shinji Ishikawa ,  Norie Matsubara ,  Masamoto Tanaka

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B23K35/28 ,  B23K35/30 ,  C22C5/06 ,  C22C5/08 ,  C22C21/00 ,  B22F7/08 ,  B23K35/02 ,  C22C19/00

CPC分类号： H01L24/32 ,  B22F7/08 ,  B22F2999/00 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/28 ,  B23K35/30 ,  B23K35/3033 ,  C22C5/06 ,  C22C5/08 ,  C22C19/00 ,  C22C21/00 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/04026 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2741 ,  H01L2224/29083 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29318 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/2949 ,  H01L2224/29639 ,  H01L2224/29644 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/83055 ,  H01L2224/83065 ,  H01L2224/83075 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8384 ,  H01L2224/85207 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00015 ,  B22F1/0018 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/0104 ,  H01L2924/01026 ,  H01L2924/01025 ,  H01L2924/01047 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/00012

摘要： The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.