公开(公告)号：US20180342598A1

公开(公告)日：2018-11-29

申请号：US15790858

申请日：2017-10-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Kan-Hsueh Tsai ,  Heng-Yuan Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/778 ,  H01L29/205 ,  H01L21/285 ,  H01L29/45

CPC classification number: H01L29/66462 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/452 ,  H01L29/7787

Abstract: A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.

公开(公告)号：US10170580B2

公开(公告)日：2019-01-01

申请号：US15790858

申请日：2017-10-23

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Kan-Hsueh Tsai ,  Heng-Yuan Lee

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L21/02 ,  H01L29/45 ,  H01L29/778 ,  H01L29/205 ,  H01L21/285

Abstract: A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.

公开(公告)号：US10074533B1

公开(公告)日：2018-09-11

申请号：US15723390

申请日：2017-10-03

Applicant: Industrial Technology Research Institute

Inventor： Po-Chun Yeh ,  Kan-Hsueh Tsai ,  Chuan-Wei Tsou ,  Heng-Yuan Lee ,  Hsueh-Hsing Liu ,  Han-Chieh Ho ,  Yi-Keng Fu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/267 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/02035 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0254 ,  H01L29/0657 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 μm and a height between 1 and 500 μm.