公开(公告)号：US09040354B2

公开(公告)日：2015-05-26

申请号：US14184856

申请日：2014-02-20

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Adolf Koller ,  Harald Seidl

IPC: H01L21/78 ,  H01L23/58 ,  H01L21/82 ,  G06F17/50

CPC classification number: H01L21/78 ,  G06F17/5068 ,  H01L21/82 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Abstract translation: 芯片包括电介质层中的电介质层和填充结构，其中填充结构沿芯片的切割边缘延伸，填充结构邻接切割边缘。

公开(公告)号：US20150069576A1

公开(公告)日：2015-03-12

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。

公开(公告)号：US10090214B2

公开(公告)日：2018-10-02

申请号：US13651496

申请日：2012-10-15

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Maria Heidenblut

IPC: H01L21/66 ,  H01L21/683

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

公开(公告)号：US09356092B2

公开(公告)日：2016-05-31

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。

公开(公告)号：US20140170836A1

公开(公告)日：2014-06-19

申请号：US14184856

申请日：2014-02-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Adolf Koller ,  Harald Seidl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  G06F17/5068 ,  H01L21/82 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Abstract translation: 芯片包括电介质层中的电介质层和填充结构，其中填充结构沿着芯片的切割边缘延伸，填充结构邻接切割边缘。

公开(公告)号：US10600701B2

公开(公告)日：2020-03-24

申请号：US16120485

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Maria Heidenblut

IPC: H01L21/66 ,  H01L21/683

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

公开(公告)号：US20180374766A1

公开(公告)日：2018-12-27

申请号：US16120485

申请日：2018-09-04

Applicant: Infineon Technologies AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Maria Heidenblut

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L21/6836 ,  H01L2221/68336

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

公开(公告)号：US20140103495A1

公开(公告)日：2014-04-17

申请号：US13651496

申请日：2012-10-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gunther Mackh ,  Gerhard Leschik ,  Maria Heidenblut

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L22/34 ,  H01L21/6836 ,  H01L2221/68336

Abstract: A wafer in accordance with various embodiments may include: at least one metallization structure including at least one opening; and at least one separation line region along which the wafer is to be diced, wherein the at least one separation line region intersects the at least one opening.

Abstract translation: 根据各种实施例的晶片可以包括：至少一个金属化结构，其包括至少一个开口; 以及要切割晶片的至少一个分离线区域，其中所述至少一个分离线区域与所述至少一个开口相交。