公开(公告)号：US10403506B2

公开(公告)日：2019-09-03

申请号：US15863954

申请日：2018-01-07

Applicant: Infineon Technologies AG

Inventor： Christoph Kamseder ,  Franco Mariani ,  Andreas Bauer ,  Thomas Fischer

IPC: H01L21/304 ,  H01L21/78 ,  H01L21/67 ,  H01L21/66

Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.

公开(公告)号：US20190214299A1

公开(公告)日：2019-07-11

申请号：US15863954

申请日：2018-01-07

Applicant: Infineon Technologies AG

Inventor： Christoph Kamseder ,  Franco Mariani ,  Andreas Bauer ,  Thomas Fischer

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/3043 ,  B28D5/022 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/34

Abstract: A method of manufacturing electronic dies by separating a wafer into electronic dies, wherein the method comprises forming a groove in the wafer with a first material removal tool having a first thickness, enlarging the groove by a second material removal tool having a second thickness larger than the first thickness, and subsequently increasing a depth of the groove by a third material removal tool having a third thickness smaller than the second thickness until the wafer is separated.

公开(公告)号：US20150069576A1

公开(公告)日：2015-03-12

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。

公开(公告)号：US20220270985A1

公开(公告)日：2022-08-25

申请号：US17582285

申请日：2022-01-24

Applicant: Infineon Technologies AG

Inventor： Sergey Ananiev ,  Andreas Bauer ,  Michael Goroll ,  Maria Heidenblut ,  Stefan Kaiser ,  Gunther Mackh ,  Kabula Mutamba ,  Reinhard Pufall ,  Georg Reuther

IPC: H01L23/00

Abstract: A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.

公开(公告)号：US09356092B2

公开(公告)日：2016-05-31

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。