公开(公告)号：US09356092B2

公开(公告)日：2016-05-31

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。

公开(公告)号：US09576875B2

公开(公告)日：2017-02-21

申请号：US14591014

申请日：2015-01-07

Applicant: Infineon Technologies AG

Inventor： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

IPC: H01L23/31 ,  H01L23/485 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract translation: 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US20150069576A1

公开(公告)日：2015-03-12

申请号：US14025185

申请日：2013-09-12

Applicant: Infineon Technologies AG

Inventor： Franco Mariani ,  Andreas Bauer ,  Reinhard Hess ,  Gerhard Leschik

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L29/06 ,  H01L21/78 ,  H01L29/0684

Abstract: A method includes providing a semiconductor wafer including multiple semiconductor chips, forming a first scribe line on a frontside of the semiconductor wafer, wherein the first scribe line has a first width and separates semiconductor chips of the semiconductor wafer, forming a second scribe line on the frontside of the semiconductor wafer, wherein the second scribe line has a second width and separates semiconductor chips of the semiconductor wafer, wherein the first scribe line and the second scribe line intersect in a crossing area which is greater than a product of the first width and the second width, and plasma etching the semiconductor wafer in the crossing area.

Abstract translation: 一种方法包括提供包括多个半导体芯片的半导体晶片，在半导体晶片的前侧形成第一划线，其中第一划线具有第一宽度并分离半导体晶片的半导体芯片，在第二划线上形成第二划线 其中所述第二划线具有第二宽度并且分离所述半导体晶片的半导体芯片，其中所述第一划线和所述第二划线在交叉区域相交，所述交叉区域大于所述第一宽度和 第二宽度，并且在交叉区域等离子体蚀刻半导体晶片。