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公开(公告)号：US10574220B2
公开(公告)日：2020-02-25
申请号：US16251315
申请日：2019-01-18
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
Abstract: A circuit for processing an input-signal voltage, and including an input capacitance coupled between an input node of the circuit and a sense node of a comparator; a reference capacitance coupled to the sense node of the comparator; and a common mode switch coupled between the sense node and a reference node of the comparator. The circuit is configured to have the input capacitance set to a reference input voltage while the common mode switch is closed, and the input node set to the input-signal voltage while the common mode switch is open. The reference capacitance includes a plurality of capacitances, at least one of which is provided as a switched capacitance that is selectively controllable to configure the plurality of capacitances. A switched capacitance controller is configured to control the switched capacitance so as to compensate, at the sense node, a comparator offset voltage.
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公开(公告)号：US10305377B2
公开(公告)日：2019-05-28
申请号：US15710502
申请日：2017-09-20
Applicant: Infineon Technologies AG
Inventor： Kyrylo Cherniak , Werner Hoellinger , Gerhard Maderbacher , Stefano Marsili , Volha Subotskaya
Abstract: Representative implementations of devices and techniques may minimize switching losses and voltage ripple in a switched capacitor de-de converter. A digital controller is used to control switching, based on an existing load. In some examples, the digital controller may insert a dead-time phase in a switching period, which may reduce voltage ripple for a low output load current. In other examples, the digital controller may adjust the conductance of a plurality of sub-switches, where the plurality of sub-switches may include one or more sub-switches that have a higher on-resistance than other sub-switches. For example, a sub-switch may have an on-resistance that is a multiple of the on-resistance of other sub-switches.
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公开(公告)号：US10187047B2
公开(公告)日：2019-01-22
申请号：US15471081
申请日：2017-03-28
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
Abstract: A circuit for processing an input-signal voltage comprises an input capacitance coupled between an input node of the circuit and a sense node of a comparator and a reference capacitance coupled to the sense node of the comparator. A method for processing an input-signal voltage comprises configuring a reference capacitance coupled to an input capacitance; during a charge phase, charging the reference capacitance to a first-level reference voltage; and, during an operative phase, setting the input capacitance to an input-signal voltage to obtain, at the sense node, a sense voltage.
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公开(公告)号：US20230283243A1
公开(公告)日：2023-09-07
申请号：US18172008
申请日：2023-02-21
Applicant: Infineon Technologies AG
Inventor： Herwig Wappis , Peter Singerl , Martin Mataln , Gerhard Maderbacher
CPC classification number: H03F1/302 , G05F3/205 , H03F1/0266
Abstract: A circuit for biasing a transistor is provided. The circuit includes an output terminal configured to be coupled to a gate terminal of the transistor and circuitry. In a first state, the circuitry is configured to output a control signal at a first voltage level for setting the transistor to a first transistor state. In a second state, the circuitry is configured to first output the control signal at a second voltage level different from the first voltage level following by changing the control signal from the second voltage level towards a third voltage level different from the first and second voltage level over time.
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公开(公告)号：US20190173460A1
公开(公告)日：2019-06-06
申请号：US16251315
申请日：2019-01-18
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
CPC classification number: H03K5/24 , H03H19/004
Abstract: A circuit for processing an input-signal voltage, and including an input capacitance coupled between an input node of the circuit and a sense node of a comparator; a reference capacitance coupled to the sense node of the comparator; and a common mode switch coupled between the sense node and a reference node of the comparator. The circuit is configured to have the input capacitance set to a reference input voltage while the common mode switch is closed, and the input node set to the input-signal voltage while the common mode switch is open. The reference capacitance includes a plurality of capacitances, at least one of which is provided as a switched capacitance that is selectively controllable to configure the plurality of capacitances. A switched capacitance controller is configured to control the switched capacitance so as to compensate, at the sense node, a comparator offset voltage.
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Patent Agency Ranking
公开(公告)号：US10224915B2
公开(公告)日：2019-03-05
申请号：US15471152
申请日：2017-03-28
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
IPC: H03M1/38 , H04N1/00 , H03F1/02 , H04B7/00 , H04L25/03 , H04N1/04 , H03M1/34 , H03K5/24 , H03H19/00
Abstract: A circuit for processing an input-signal voltage comprises a first comparator comprising a first-comparator sense node and a reference capacitance that is coupled to the first-comparator sense node, a second comparator comprising a second-comparator sense node, and a comparator select switch coupled between a path input terminal of the circuit and the first-comparator sense node and the second-comparator sense node. A method of processing at least one input-signal voltage using at least one associated threshold voltage in a circuit, wherein a plurality of comparators comprises more comparators than there are path input terminals coupled to path output terminals, comprises selectively making a coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal, while breaking the coupling via the other comparator.
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公开(公告)号：US20180013342A1
公开(公告)日：2018-01-11
申请号：US15710502
申请日：2017-09-20
Applicant: Infineon Technologies AG
Inventor： Kyrylo Cherniak , Werner Hoellinger , Gerhard Maderbacher , Stefano Marsili , Volha Subotskaya
CPC classification number: H02M3/07 , H02M1/14 , H02M2001/0054 , Y02B70/1491
Abstract: Representative implementations of devices and techniques may minimize switching losses and voltage ripple in a switched capacitor de-de converter. A digital controller is used to control switching, based on an existing load. In some examples, the digital controller may insert a dead-time phase in a switching period, which may reduce voltage ripple for a low output load current. In other examples, the digital controller may adjust the conductance of a plurality of sub-switches, where the plurality of sub-switches may include one or more sub-switches that have a higher on-resistance than other sub-switches. For example, a sub-switch may have an on-resistance that is a multiple of the on-resistance of other sub-switches.
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公开(公告)号：US09780655B2
公开(公告)日：2017-10-03
申请号：US14685911
申请日：2015-04-14
Applicant: INFINEON TECHNOLOGIES AG
Inventor： Stefano Marsili , Werner Hoellinger , Gerhard Maderbacher
Abstract: Representative implementations of devices and techniques minimize switching losses in a switched capacitor dc-dc converter. The slope of the charging and/or discharging phase may be modified, smoothing the transitions from charge to discharge and/or discharge to charge of the switched capacitor.
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公开(公告)号：US20170294905A1
公开(公告)日：2017-10-12
申请号：US15471152
申请日：2017-03-28
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
CPC classification number: H03K5/24 , H03H19/004
Abstract: A circuit for processing an input-signal voltage comprises a first comparator comprising a first-comparator sense node and a reference capacitance that is coupled to the first-comparator sense node, a second comparator comprising a second-comparator sense node, and a comparator select switch coupled between a path input terminal of the circuit and the first-comparator sense node and the second-comparator sense node. A method of processing at least one input-signal voltage using at least one associated threshold voltage in a circuit, wherein a plurality of comparators comprises more comparators than there are path input terminals coupled to path output terminals, comprises selectively making a coupling via one comparator of two comparators provided in parallel to form a coupling path from the path input terminal to an associated path output terminal, while breaking the coupling via the other comparator.
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公开(公告)号：US20170294904A1
公开(公告)日：2017-10-12
申请号：US15471081
申请日：2017-03-28
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Gerhard Maderbacher
CPC classification number: H03K5/24 , H03H19/004
Abstract: A circuit for processing an input-signal voltage comprises an input capacitance coupled between an input node of the circuit and a sense node of a comparator and a reference capacitance coupled to the sense node of the comparator. A method for processing an input-signal voltage comprises configuring a reference capacitance coupled to an input capacitance; during a charge phase, charging the reference capacitance to a first-level reference voltage; and, during an operative phase, setting the input capacitance to an input-signal voltage to obtain, at the sense node, a sense voltage.
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