公开(公告)号：US20180375801A1

公开(公告)日：2018-12-27

申请号：US15776661

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Albert S. CHENG

IPC: H04L12/931 ,  H04L12/801

Abstract: Apparatuses and methods associated with distributing congestion information in a switch are provided. In embodiments, the switch includes a plurality of ports arranged in a plurality of rows and a plurality of columns. The switch further includes a plurality of daisy-chain buses, individual daisy-chain buses coupling the ports of a respective row to one another in a daisy-chain. The switch further includes a plurality of column buses, individual column buses coupling an individual port of the plurality of ports to the other ports of the respective column. Individual ports of a respective row receive congestion information from the other ports of the row via the respective daisy-chain bus and pass the congestion information to the other ports of the respective column via the respective column bus. Other embodiments may be described and/or claimed.

公开(公告)号：US20180287953A1

公开(公告)日：2018-10-04

申请号：US15531692

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Michael A. PARKER ,  Thomas D. LOVETT ,  Steven F. HOOVER

IPC: H04L12/863

Abstract: Apparatuses, methods and storage medium associated with the placement of data packets in one or more queues of a switch are described herein. In embodiments, the switch may include a plurality of virtual lane (VL) queues (VLQs) and a plurality of generic queues (GQs). A queue manager may be configured to selectively place a packet of a particular VL in a corresponding VLQ or a GQ. Other embodiments may be described and/or claimed.

公开(公告)号：US20170339103A1

公开(公告)日：2017-11-23

申请号：US15531153

申请日：2014-12-27

Applicant: INTEL CORPORATION

Inventor： Todd M. RIMMER ,  Albert S. CHENG

IPC: H04L29/12 ,  H04L12/761 ,  H04L12/931 ,  H04L29/06

CPC classification number: H04L61/2069 ,  H04L12/6418 ,  H04L45/16 ,  H04L49/358 ,  H04L61/6095 ,  H04L69/22

Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.

公开(公告)号：US20200050569A1

公开(公告)日：2020-02-13

申请号：US16473561

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gaspar MORA PORTA ,  Michael A PARKER ,  Roberto PENARANDA CEBRIAN ,  Albert S. CHENG ,  Francesc GUIM BERNAT

IPC: G06F13/40 ,  H04L12/801 ,  H04L12/937 ,  G06F13/366

Abstract: In some embodiments, the invention involves using a weighted arbiter switch to provide fairness in passing input streams through a plurality of input ports to an output port. The weighted arbiter switches may be combined in a hierarchical architecture to enable routing through many levels of switches. Each input port has an associated flow counter to count input stream traffic through the input port. An arbiter switch uses the flow counts and weights from arbiter switches at a lower level in the hierarchy to generate a fairly distributed routing of input streams through the output port. Other embodiments are described and claimed.

公开(公告)号：US20180287963A1

公开(公告)日：2018-10-04

申请号：US15531643

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael A. PARKER ,  Steven F. HOOVER ,  Gregory J. HUBBARD

IPC: H04L12/933 ,  H04L12/937

CPC classification number: H04L49/101 ,  H04L49/107 ,  H04L49/109 ,  H04L49/254

Abstract: Apparatuses, methods and storage media associated with multiple multi-drop buses in a switch are provided herein. In some embodiments, the switch may include a multi-drop row bus to transmit a plurality of frames in a row dimension of the matrix switch and a multi-drop column bus to transmit the plurality of frames in a column dimension of the matrix switch. The switch may further include an input port to receive the plurality of frames and an output port to output the plurality of frames from the matrix switch. Other embodiments may be described and/or claimed.

公开(公告)号：US20170339071A1

公开(公告)日：2017-11-23

申请号：US15531688

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael A. PARKER

IPC: H04L12/947 ,  H04L12/835 ,  H04L12/741 ,  H04L12/801 ,  H04L12/935 ,  H04L12/933

Abstract: Apparatuses, methods and storage medium associated with routing data in a switch are provided. In embodiments, the switch may include route lookup circuitry determine a first set of output ports that are available to send a data packet to a destination node. The lookup circuitry may further select, based on respective congestion levels associated with the first set of output ports, a plurality of output ports for a second set of output ports from the first set of output ports. An input queue of the switch may buffer the data packet and route information associated with the second set of output ports. The switch may further include route selection circuitry to select a destination output port from the second set of output ports, based on updated congestion levels associated with the output ports of the second set of output ports. Other embodiments may be described and/or claimed.

公开(公告)号：US20170295112A1

公开(公告)日：2017-10-12

申请号：US15531694

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Albert S. CHENG ,  Thomas D. LOVETT ,  Michael S. PARKER ,  Steven F. HOOVER

IPC: H04L12/935 ,  H04L12/937

CPC classification number: H04L49/3036 ,  H04L12/6418 ,  H04L49/101 ,  H04L49/103 ,  H04L49/254 ,  H04L49/505 ,  H04L49/9036

Abstract: Apparatuses, methods and storage medium associated with buffering data in a switch are provided. In embodiments, the switch may include a plurality of queue buffers, a plurality of queues respectively associated with the plurality of queue buffers, a shared buffer, and a queue point controller coupled with the plurality of queue buffers and the shared buffer. In embodiments the queue point controller may be configured to determine an amount of available space in a selected queue buffer of the plurality of queue buffers. The queue point controller may be further configured to allocate at least a portion of the shared buffer to a selected queue that is associated with the selected queue buffer. In embodiments, this allocation may be based on the amount of available space determined in the selected queue buffer. Other embodiments may be described and/or claimed.