公开(公告)号：US20200249980A1

公开(公告)日：2020-08-06

申请号：US16855139

申请日：2020-04-22

Applicant: Intel Corporation

Inventor： Bishwajit DUTTA ,  Sanjeev N. TRIKA ,  Anand S. RAMALINGAM ,  Pallav H. GALA

IPC: G06F9/46 ,  G06F9/54 ,  G06F9/48 ,  G06F3/06

Abstract: Examples include techniques for managing high priority (HP) and low priority (LP) write transaction requests by a storage device. An embodiment includes receiving, at a storage controller for a storage device, a write transaction request from a requestor to write data to one or more memory devices in the storage device. When the write transaction request is for a high priority (HP) write, coalescing the write data into a transaction buffer in a memory of the storage device, sending an acknowledgment for the write transaction request to the requestor, and writing the write data into the one or more memory devices. When the write transaction request is for a low priority (LP) write, writing the write data into the one or more memory devices, and then sending an acknowledgment for the write transaction request to the requestor.

公开(公告)号：US20180285155A1

公开(公告)日：2018-10-04

申请号：US15475017

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Anand S. RAMALINGAM

IPC: G06F9/48 ,  G06F11/07

CPC classification number: G06F11/0736 ,  G06F9/30101 ,  G06F11/0757 ,  G06F11/0772

Abstract: A hardware acceleration block is configured to process via a dedicated pair of registers, a plurality of commands of each of a plurality of threads received from a compute complex. The hardware acceleration block receives successive commands that are separated by at least an amount of time, from a thread of the plurality of threads. The amount of time is adequate to process a command from the thread.

公开(公告)号：US20180173418A1

公开(公告)日：2018-06-21

申请号：US15385791

申请日：2016-12-20

Applicant: INTEL CORPORATION

Inventor： Peng LI ,  Anand S. RAMALINGAM ,  Jawad B. KHAN ,  William K. LUI ,  Divya NARAYANAN ,  Sanjeev N. TRIKA

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0688

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

公开(公告)号：US20210216239A1

公开(公告)日：2021-07-15

申请号：US17214819

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Bishwajit DUTTA ,  Anand S. RAMALINGAM ,  Sanjeev N. TRIKA ,  Pallav H. GALA

IPC: G06F3/06 ,  G06F12/02

Abstract: Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.

公开(公告)号：US20180088810A1

公开(公告)日：2018-03-29

申请号：US15276696

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2212/70 ,  G06F2212/7211

Abstract: A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.

公开(公告)号：US20180121092A1

公开(公告)日：2018-05-03

申请号：US15723072

申请日：2017-10-02

Applicant: INTEL CORPORATION

Inventor： Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/00

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201

Abstract: A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.

公开(公告)号：US20160179376A1

公开(公告)日：2016-06-23

申请号：US14581723

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/7201

Abstract: A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.

Abstract translation: 固态驱动器的控制器启动对存储在固态驱动器的非易失性存储器中的数据的重新包装，其中在重新包装数据期间执行存储在固态驱动器的非易失性存储器中的数据的刷新 存储在固态驱动器的非易失性存储器中。 在存储在固态驱动器的非易失性存储器中的数据被重新包装的同时，逻辑块在固态驱动器的非易失性存储器的预擦除位置中以递增的顺序物理地连续放置。

公开(公告)号：US20160092117A1

公开(公告)日：2016-03-31

申请号：US14499016

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Anand S. RAMALINGAM ,  Vasantha M. SRIRANJANI

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0679

Abstract: Provided are a method and system for allocating read requests in a solid state drive coupled to a host. An arbiter in the solid state drive determines which of a plurality of channels in the solid state drive is a lightly loaded channel of a plurality of channels. Resources for processing one or more read requests intended for the determined lightly loaded channel are allocated, wherein the one or more read requests have been received from the host. The one or more read requests are placed in the determined lightly loaded channel for the processing. In certain embodiments, the lightly loaded channel is the most lightly loaded channel of the plurality of channels.

Abstract translation: 提供了一种用于在耦合到主机的固态驱动器中分配读取请求的方法和系统。 固态驱动器中的仲裁器确定固态驱动器中的多个通道中的哪一个是多个通道的轻负载通道。 分配处理用于确定的轻载信道的一个或多个读取请求的资源，其中从主机接收到一个或多个读取请求。 一个或多个读请求被放置在确定的轻载信道中用于处理。 在某些实施例中，轻装载的通道是多个通道中最轻的加载通道。

公开(公告)号：US20190042146A1

公开(公告)日：2019-02-07

申请号：US16054983

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Michal WYSOCZANSKI ,  Kapil KARKRA ,  Piotr WYSOCKI ,  Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38

Abstract: A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

公开(公告)号：US20160283116A1

公开(公告)日：2016-09-29

申请号：US14671968

申请日：2015-03-27

Applicant: INTEL CORPORATION

Inventor： Anand S. RAMALINGAM

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F3/0602 ,  G06F3/0611 ,  G06F3/0629 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F12/0895 ,  G06F13/16 ,  G06F2212/202 ,  G06F2212/60

Abstract: In one embodiment, sequential write stream management is employed to improve the sequential nature of write data placed in a storage such as a solid state drive, notwithstanding intermingling of write commands from various sequential and nonsequential streams from multiple processor nodes in a system. In one embodiment, write data from an identified sequential write stream is placed in a storage area assigned to that particular identified sequential write stream. In another aspect, detected sequential write streams are identified as a function of write velocity of the detected stream. Other aspects are described herein.

Abstract translation: 在一个实施例中，尽管来自系统中来自多个处理器节点的各种顺序和非顺序流的写入命令的混合，采用顺序写入流管理来改善放置在诸如固态驱动器的存储器中的写入数据的顺序特性。 在一个实施例中，将从所识别的顺序写入流写入数据放置在分配给该特定识别顺序写入流的存储区域中。 在另一方面，检测到的顺序写入流被识别为检测到的流的写入速度的函数。 本文描述了其它方面。