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公开(公告)号：US20190087382A1
公开(公告)日：2019-03-21
申请号：US15749008
申请日：2016-12-30
Applicant: INTEL CORPORATION
Inventor： Qiuhua HU , Jie CHEN , Hua HE , Ke HAN , Arvind KUMAR
CPC classification number: G06F13/4291 , G06F13/38 , G06F13/385 , G06F2213/0016
Abstract: Embodiments of the present disclosure provide for an apparatus for facilitating a connection with an external sensor module, in accordance with some embodiments. In one instance, the apparatus may include a processor and a sensor hub coupled with the processor, wherein the sensor hub may include a bus to provide a connection between the apparatus and the external sensor module. The apparatus may further include signal pattern generation circuitry coupled with the sensor hub to generate a signal pattern in response to a connection of the external sensor module to the apparatus via the bus or disconnect of the external sensor module from the bus, to indicate an insert or remove event to the apparatus, and facilitate the connection of the apparatus with the external sensor module. Other embodiments may be described and/or claimed.
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公开(公告)号：US20200233821A1
公开(公告)日：2020-07-23
申请号：US16827205
申请日：2020-03-23
Applicant: Intel Corporation
Inventor： Arvind KUMAR , Dean-Dexter R. EUGENIO , John R. GOLES
Abstract: An N-bit bus includes (N−1) bidirectional interfaces to couple to (N−1) bidirectional signal lines to exchange (transmit and receive) signals between companion devices. The bus includes two unidirectional signal line interfaces. The first is a unidirectional receive interface to couple to a unidirectional signal line to receive signals from the companion device. The second is a unidirectional transmit interface to couple to a unidirectional signal line to transmit signals to the companion device. The bus provides N signal lines for the N-bit bus in each direction, with an additional “backwards facing” signal line. The backwards facing signal line can allow the devices to prepare for a switch in the direction of the N-bit bus.
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公开(公告)号：US20180136866A1
公开(公告)日：2018-05-17
申请号：US15811497
申请日：2017-11-13
Applicant: Intel Corporation
Inventor： Dean-Dexter R. EUGENIO , Arvind KUMAR , John R. GOLES , Christopher E. COX
CPC classification number: G06F3/0635 , G06F3/0679 , G06F11/22 , G06F13/1673 , G06F13/1689
Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
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公开(公告)号：US20210326041A1
公开(公告)日：2021-10-21
申请号：US17359423
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Arvind KUMAR , Dean-Dexter R. EUGENIO , John R. GOLES , Santhosh MUSKULA
Abstract: In a memory system, reference voltage training per path provides the capability to train receiver and transmitter reference voltages to optimal values based on selected feedback per path from the memory device. Training receiver reference voltages to an optimal receiver reference voltage per path includes programming dedicated mode registers that enable a local receiver voltage reference adjuster circuit to adjust the receiver reference voltage per path to the optimal receiver reference voltage per path. Transmitter reference voltage training includes the capability to also train an optimal input timing delay for an optimal transmitter reference voltage. Reference voltage training can be performed by a host component and/or a test system having access to the selected feedback per path of the memory device undergoing training.
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Patent Agency Ranking
公开(公告)号：US20200159429A1
公开(公告)日：2020-05-21
申请号：US16702359
申请日：2019-12-03
Applicant: Intel Corporation
Inventor： Dean-Dexter R. EUGENIO , Arvind KUMAR , John R. GOLES , Christopher E. COX
Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
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公开(公告)号：US20160282129A1
公开(公告)日：2016-09-29
申请号：US14368350
申请日：2013-12-19
Applicant: INTEL CORPORATION
Inventor： Ren WANG , Zhongghong OU , Arvind KUMAR , Kristoffer FLEMING , Tsung-Yuan C. TAI , Timothy J. GRESHAM , John C. WEAST , Corey KUKIS
IPC: G01C21/34 , H04W24/08 , H04B17/318 , H04W4/02
CPC classification number: G01C21/34 , G01C21/3446 , G01C21/3453 , H04B17/318 , H04W4/02 , H04W24/08
Abstract: Technologies for providing information to a user while traveling include a mobile computing device to determine network condition information associated with a route segment. The route segment may be one of a number of route segments defining at least one route from a starting location to a destination. The mobile computing device may determine a route from the starting location to the destination based on the network condition information. The mobile computing device may upload the network condition information to a crowdsourcing server. A mobile computing device may predict a future location of the device based on device context, determine a safety level for the predicted location, and notify the user if the safety level is below a threshold safety level. The device context may include location, time of day, and other data. The safety level may be determined based on predefined crime data. Other embodiments are described and claimed.
Abstract translation: 在旅行时向用户提供信息的技术包括移动计算设备以确定与路线段相关联的网络状况信息。 路线段可以是定义从起始位置到目的地的至少一条路线的多个路段中的一个。 移动计算设备可以基于网络条件信息来确定从起始位置到目的地的路由。 移动计算设备可以将网络条件信息上传到众包服务器。 移动计算设备可以基于设备上下文来预测设备的未来位置，确定预测位置的安全级别，并且如果安全级别低于阈值安全级别则通知用户。 设备上下文可以包括位置，时间和其他数据。 可以基于预定义的犯罪数据来确定安全级别。 描述和要求保护其他实施例。
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公开(公告)号：US20210390991A1
公开(公告)日：2021-12-16
申请号：US17354788
申请日：2021-06-22
Applicant: Intel Corporation
Inventor： Arvind KUMAR , Dean-Dexter R. EUGENIO , Santhosh MUSKULA
Abstract: Methods and apparatus for duty cycle adjuster optimization training algorithms to minimize jitter associated with DDR5 DRAM transmitters. Basic and Advanced Duty Cycle Adjuster (DCA) training algorithms are implemented to reduce duty cycle error and hence reduce phase mismatch translated jitter in the transmitter DQS signals. In accordance with aspects of the Basic DCA training algorithm, duty cycles for QCLK, IBQCLK, and QBCLK are adjusted by a memory controller that utilizes a DCA function implemented on a memory module (e.g., DDR5 SDRAM DIMM) to obtain a first set of optimized DCA code settings. The first set of optimized DCA code settings are then used as initial settings for the Advance DCA training algorithm to further optimize the DCA code settings for QCLK, IBQCLK, and QBCLK. A similar technical may be employed to reduce duty cycle error and jitter for DQ signals.
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公开(公告)号：US20210327524A1
公开(公告)日：2021-10-21
申请号：US17359442
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Arvind KUMAR , Dean-Dexter R. EUGENIO , John R. GOLES
Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.
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公开(公告)号：US20210247919A1
公开(公告)日：2021-08-12
申请号：US17221728
申请日：2021-04-02
Applicant: Intel Corporation
Inventor： Dean-Dexter R. EUGENIO , Arvind KUMAR , John R. GOLES , Christopher E. COX
Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.
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