公开(公告)号：US20220139843A1

公开(公告)日：2022-05-05

申请号：US17428565

申请日：2019-04-10

Applicant: INTEL CORPORATION

Inventor： Jun LU ,  Wei LIAO ,  Chen ZHANG ,  Guangying ZHANG ,  Liguang DU ,  Chuansheng LIU ,  Michael LEDDIGE ,  Weimin SHI ,  Eduardo MICHEL ,  Guillermo RENTERIA ZAMUDIO

IPC: H01L23/552 ,  H01L23/00

Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one electromagnetic interference structure attached to the electronic substrate adjacent to the at least one integrated circuit device. The at least one electromagnetic interference structure may be electrically attached to the electronic substrate with at least one resilient connector extending therebetween. In one embodiment, the at least one electromagnetic interference structure may be grounded to the electronic substrate.

公开(公告)号：US20240421025A1

公开(公告)日：2024-12-19

申请号：US18290289

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Lianchang DU ,  Jeffory L. SMALLEY ,  Srikant NEKKANTY ,  Eric W. BUDDRIUS ,  Yi ZENG ,  Xinjun ZHANG ,  Maoxin YIN ,  Zhichao ZHANG ,  Chen ZHANG ,  Yuehong FAN ,  Mingli ZHOU ,  Guoliang YING ,  Yinglei REN ,  Chong J. ZHAO ,  Jun LU ,  Kai WANG ,  Timothy Glen HANNA ,  Vijaya K. BODDU ,  Mark A. SCHMISSEUR ,  Lijuan FENG

IPC: H01L23/367 ,  H01L23/538 ,  H01L25/065 ,  H01R13/627

Abstract: A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.

公开(公告)号：US20240314973A1

公开(公告)日：2024-09-19

申请号：US18671881

申请日：2024-05-22

Applicant: Intel Corporation

Inventor： Chen ZHANG ,  Xiang QUE ,  Yang YAO ,  Yuehong FAN ,  Guangying ZHANG ,  Liguang DU ,  Shaorong ZHOU ,  Chuanlou WANG ,  Yingqiong BU ,  Yue YANG

IPC: H05K7/20 ,  H05K1/02

CPC classification number: H05K7/20236 ,  H05K1/0203 ,  H05K7/20272 ,  H05K7/20281 ,  H05K7/20409 ,  H05K7/20763 ,  H05K7/20263

Abstract: An apparatus is described that includes an immersion bath chamber and a cover that is to seal the immersion bath chamber. An apparatus is described that includes an immersion bath chamber and an installable/removable transfer member. The installable/removable transfer member has fluidic connectors designed to couple to respective warmed fluid flow output ports of pluggable units to be cooled in the immersion bath chamber and having respective backplane interface designs. An apparatus is described that includes an immersion bath chamber and an overflow chamber. The overflow chamber is to receive an overflow of liquid coolant from the immersion bath chamber, wherein a first exit flow channel from the overflow chamber is coupled to a second exit fluid flow channel from the immersion bath chamber through a valve, wherein, an opening of the valve is controllable to vary a gravitational fluid flow within the immersion bath chamber.