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公开(公告)号:US20170123703A1
公开(公告)日:2017-05-04
申请号:US15357783
申请日:2016-11-21
Applicant: Intel Corporation
Inventor: JASON B. AKERS , KNUT S. GRIMSRUD , ROBERT J. ROYER, JR. , RICHARD P. MANGOLD , SANJEEV N. TRIKA
CPC classification number: G06F3/0625 , G06F1/3287 , G06F3/0655 , G06F3/0688 , G06F11/1417 , G11C5/148 , G11C7/1072 , G11C14/0009 , Y02D10/171
Abstract: Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
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公开(公告)号:US20190102565A1
公开(公告)日:2019-04-04
申请号:US15721554
申请日:2017-09-29
Applicant: INTEL CORPORATION
Inventor: JAMES A. BOYD , DALE J. JUENEMANN , ROBERT J. ROYER, JR.
Abstract: Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.
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公开(公告)号:US20180307263A1
公开(公告)日:2018-10-25
申请号:US15960074
申请日:2018-04-23
Applicant: INTEL CORPORATION
Inventor: ANOOP MUKKER , ENG HUN OOI , ROBERT J. ROYER, JR. , BRIAN R. MCFARLANE
CPC classification number: G06F1/08 , G06F1/12 , G06F13/40 , G06F13/4291 , H04J3/0697
Abstract: The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.
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公开(公告)号:US20170336978A1
公开(公告)日:2017-11-23
申请号:US15618170
申请日:2017-06-09
Applicant: Intel Corporation
Inventor: BLAISE FANNING , MARK A. SCHMISSEUR , RAYMOND S. TETRICK , ROBERT J. ROYER, JR. , DAVID B. MINTURN , SHANE MATTHEWS
CPC classification number: G06F3/0604 , G06F3/0629 , G06F3/0632 , G06F3/0634 , G06F3/0644 , G06F3/0664 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F13/16 , G06F13/28 , G06F2212/7206
Abstract: Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration commands may be received at a controller for an SSD having one or more non-volatile memory arrays. The SSD may be configured to operate in at least one of a storage mode, a memory mode or a combination of the storage mode or the memory mode based on the one or more configuration commands. Other examples are described and claimed.
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公开(公告)号:US20170090509A1
公开(公告)日:2017-03-30
申请号:US14866237
申请日:2015-09-25
Applicant: Intel Corporation
Inventor: ANOOP MUKKER , ENG HUN OOI , ROBERT J. ROYER, JR. , BRIAN R. MCFARLANE
CPC classification number: G06F1/08 , G06F1/12 , G06F13/40 , G06F13/4291 , H04J3/0697
Abstract: These present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negation component to negotiate a shift in an operating frequency with other component on an interface where the different component have non-common clocks.
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