公开(公告)号：US20150171012A1

公开(公告)日：2015-06-18

申请号：US14630572

申请日：2015-02-24

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Hui Jae YOO ,  Yan A. BORODOVSKY ,  Florian GSTREIN ,  David N. SHYKIND ,  Kevin L. LIN

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract translation: 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。