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    STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
    2.
    发明公开
    STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH 审中-公开

    公开(公告)号：US20240145557A1

    公开(公告)日：2024-05-02

    申请号：US18408346

    申请日：2024-01-09

    Applicant: Intel Corporation

    Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Cheng-Ying HUANG ,  Gilbert DEWEY

    IPC: H01L29/417

    CPC classification number: H01L29/41741 ,  H01L29/41775

    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

    COMPUTE NEAR MEMORY WITH BACKEND MEMORY
    5.
    发明申请
    COMPUTE NEAR MEMORY WITH BACKEND MEMORY 有权

    公开(公告)号：US20220165735A1

    公开(公告)日：2022-05-26

    申请号：US17670248

    申请日：2022-02-11

    Applicant: Intel Corporation

    Inventor： Abhishek SHARMA ,  Noriyuki SATO ,  Sarah ATANASOV ,  Huseyin Ekin SUMBUL ,  Gregory K. CHEN ,  Phil KNAG ,  Ram KRISHNAMURTHY ,  Hui Jae YOO ,  Van H. LE

    IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096

    Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

    SELF-ALIGNED REPEATEDLY STACKABLE 3D VERTICAL RRAM
    7.
    发明申请
    SELF-ALIGNED REPEATEDLY STACKABLE 3D VERTICAL RRAM 审中-公开

    公开(公告)号：US20200006427A1

    公开(公告)日：2020-01-02

    申请号：US16024684

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Noriyuki SATO ,  Kevin O'BRIEN ,  Eungnak HAN ,  Manish CHANDHOK ,  Gurpreet SINGH ,  Nafees KABIR ,  Kevin LIN ,  Rami HOURANI ,  Abhishek SHARMA ,  Hui Jae YOO

    IPC: H01L27/24 ,  H01L45/00

    Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
    8.
    发明申请
    BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20240371700A1

    公开(公告)日：2024-11-07

    申请号：US18774351

    申请日：2024-07-16

    Applicant: Intel Corporation

    Inventor： Aaron D. LILAK ,  Ehren MANNEBACH ,  Anh PHAN ,  Richard E. SCHENKER ,  Stephanie A. BOJARSKI ,  Willy RACHMADY ,  Patrick R. MORROW ,  Jeffrey D. BIELEFELD ,  Gilbert DEWEY ,  Hui Jae YOO

    IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/532 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

    Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

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