公开(公告)号：US20190318959A1

公开(公告)日：2019-10-17

申请号：US16346305

申请日：2016-12-23

申请人： Intel Corporation

发明人： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/311

摘要： Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

申请人： Intel Corporation

发明人： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC分类号： G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

摘要： Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20200335434A1

公开(公告)日：2020-10-22

申请号：US16389672

申请日：2019-04-19

申请人： Intel Corporation

发明人： Marie KRYSAK ,  Kevin L. LIN ,  Robert BRISTOL ,  Charles H. WALLACE

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L21/027

摘要： Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

公开(公告)号：US20220262722A1

公开(公告)日：2022-08-18

申请号：US17735006

申请日：2022-05-02

申请人： Intel Corporation

发明人： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

摘要： Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20190318958A1

公开(公告)日：2019-10-17

申请号：US16317015

申请日：2016-09-30

申请人： Intel Corporation

发明人： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL ,  Rami HOURANI ,  Eungnak HAN

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/311

摘要： Approaches based on photobucket floor colors with selective grafting for semiconductor structure fabrication, and the resulting structures, are described. For example, a grating structure is formed above an ILD layer formed above a substrate, the grating structure including a plurality of dielectric spacers separated by alternating first trenches and second trenches, grafting a resist-inhibitor layer in the first trenches but not in the second trenches, forming photoresist in the first trenches and in the second trenches, exposing and removing the photoresist in select ones of the second trenches to a lithographic exposure to define a set of via locations, etching the set of via locations into the ILD layer, and forming a plurality of metal lines in the ILD layer, where select ones of the plurality of metal lines includes an underlying conductive via corresponding to the set of via locations.

公开(公告)号：US20220130719A1

公开(公告)日：2022-04-28

申请号：US17568648

申请日：2022-01-04

申请人： Intel Corporation

发明人： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/311

摘要： Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210225698A1

公开(公告)日：2021-07-22

申请号：US17218080

申请日：2021-03-30

申请人： Intel Corporation

发明人： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC分类号： H01L21/768 ,  H01L23/528

摘要： Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20210082800A1

公开(公告)日：2021-03-18

申请号：US17110215

申请日：2020-12-02

申请人： Intel Corporation

发明人： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

摘要： Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20150171012A1

公开(公告)日：2015-06-18

申请号：US14630572

申请日：2015-02-24

申请人： INTEL CORPORATION

发明人： Manish CHANDHOK ,  Hui Jae YOO ,  Yan A. BORODOVSKY ,  Florian GSTREIN ,  David N. SHYKIND ,  Kevin L. LIN

IPC分类号： H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

摘要翻译： 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

申请人： Intel Corporation

发明人： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC分类号： H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

摘要： Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.