公开(公告)号：US20180033593A1

公开(公告)日：2018-02-01

申请号：US15555447

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY

IPC: H01J37/304 ,  H01L23/544 ,  H01J37/04 ,  H01J37/09 ,  H01J37/317

CPC classification number: H01J37/3045 ,  H01J37/045 ,  H01J37/09 ,  H01J37/20 ,  H01J37/244 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0453 ,  H01J2237/24475 ,  H01J2237/24578 ,  H01J2237/2817 ,  H01L21/0277 ,  H01L21/0337 ,  H01L21/31144 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54473

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of fine alignment of an e-beam tool includes projecting an electron image of a plurality of apertures of an e-beam column over an X-direction alignment feature of a wafer while moving the wafer along the Y-direction. The method also includes detecting a time-resolved back-scattered electron (BSE) detection response waveform during the projecting. The method also includes determining an X-position of every edge of every feature of the X-direction alignment feature by calculating a derivative of the BSE detection response waveform. The method also includes, subsequent to determining an X-position of every edge of every feature of the X-direction alignment feature, adjusting an alignment of the e-beam column to the wafer.

公开(公告)号：US20190155160A1

公开(公告)日：2019-05-23

申请号：US16252427

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: G03F7/20 ,  H01L21/311 ,  H01L21/027 ,  H01J37/317

CPC classification number: G03F7/2037 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The first and second columns of openings together form an array having a pitch in the first direction. A scan direction of the BAA is along a second direction, orthogonal to the first direction. The pitch of the array corresponds to half of a minimal pitch layout of a target pattern of lines for orientation parallel with the second direction.

公开(公告)号：US20180143526A1

公开(公告)日：2018-05-24

申请号：US15873782

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: G03F1/20 ,  H01J37/04 ,  H01J37/302 ,  H01J37/317 ,  G03F7/20 ,  H01L21/768

CPC classification number: G03F1/20 ,  G03F7/203 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/76802

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.

公开(公告)号：US20170076905A1

公开(公告)日：2017-03-16

申请号：US15122400

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: H01J37/04 ,  G03F7/20 ,  H01L21/768 ,  G03F1/20 ,  H01J37/317 ,  H01J37/302

CPC classification number: G03F1/20 ,  G03F7/203 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/76802

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool is described. The BAA includes three distinct aperture arrays of different pitch.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，描述了用于电子束工具的遮光器孔径阵列（BAA）。 BAA包括三个不同节距的不同孔径阵列。

公开(公告)号：US20170077029A1

公开(公告)日：2017-03-16

申请号：US15122396

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Yan A. BORODOVSKY ,  Mark C. PHILLIPS

IPC: H01L23/528 ,  H01L27/11 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L23/5283 ,  H01J37/045 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76886 ,  H01L27/0207 ,  H01L27/11

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a metallization layer of an integrated circuit includes a first region having a plurality of unidirectional lines of a first width and a first pitch and parallel with a first direction. The layout also includes a second region having a plurality of unidirectional lines of a second width and a second pitch and parallel with the first direction, the second width and the second pitch different than the first width and the first pitch, respectively. The layout also includes a third region having a plurality of unidirectional lines of a third width and a third pitch and parallel with the first direction, the third width and the third pitch different than the first and second widths and different than the first and second pitches.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，集成电路的金属化层的布局包括具有第一宽度和第一间距的多个单向线并与第一方向平行的第一区域。 布局还包括具有第二宽度和第二间距的多个单向线并且与第一方向平行的第二区域，第二宽度和第二间距分别与第一宽度和第一间距不同的第二区域。 布局还包括具有第三宽度和第三间距的多个单向线并且与第一方向平行的第三区域，第三宽度和第三间距不同于第一和第二宽度并且不同于第一和第二间距 。

公开(公告)号：US20170076967A1

公开(公告)日：2017-03-16

申请号：US15122792

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: H01L21/68

CPC classification number: H01L21/682 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/24578 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，位于电子束工具的台上的晶片的实时对准的方法涉及从电子束工具的电子束列的电子束列中收集来自晶片的底层图案化特征的反向散射电子， 扫描舞台。 收集由放置在电子束柱底部的电子检测器进行。 该方法还涉及基于收集来执行阶段相对于电子束列的对准的线性校正。

公开(公告)号：US20150171012A1

公开(公告)日：2015-06-18

申请号：US14630572

申请日：2015-02-24

Applicant: INTEL CORPORATION

Inventor： Manish CHANDHOK ,  Hui Jae YOO ,  Yan A. BORODOVSKY ,  Florian GSTREIN ,  David N. SHYKIND ,  Kevin L. LIN

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including patterning a thickness dimension of an interconnect material into a thickness dimension for a wiring line with one or more vias extending from the wiring line and introducing a dielectric material on the interconnect material. A method including depositing and patterning an interconnect material into a wiring line and one or more vias; and introducing a dielectric material on the interconnect material such that the one or more vias are exposed through the dielectric material. An apparatus including a first interconnect layer in a first plane and a second interconnect in a second plane on a substrate; and a dielectric layer separating the first and second interconnect layers, wherein the first interconnect layer comprises a monolith including a wiring line and at least one via, the at least one via extending from the wiring line to a wiring line of the second interconnect layer.

Abstract translation: 一种方法，包括将互连材料的厚度尺寸图案化为具有从布线延伸的一个或多个通孔的布线的厚度尺寸，并将介电材料引入到互连材料上。 一种包括将互连材料沉积和图案化成布线和一个或多个通孔的方法; 以及在所述互连材料上引入介电材料，使得所述一个或多个通孔通过所述介电材料暴露。 一种装置，包括在第一平面中的第一互连层和在衬底上的第二平面中的第二互连; 以及分离所述第一和第二互连层的电介质层，其中所述第一互连层包括包括布线和至少一个通孔的整体，所述至少一个通孔从所述布线延伸到所述第二互连层的布线。

公开(公告)号：US20170338105A1

公开(公告)日：2017-11-23

申请号：US15528329

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Shakul TANDON ,  Yan A. BORODOVSKY ,  Charles H. WALLACE ,  Paul A. NYHUS

IPC: H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  G03F7/11 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/0277 ,  G03F7/093 ,  G03F7/11 ,  G03F7/2059 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823431

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. Particular embodiments are directed to implementation of an underlying absorbing and/or conducting layer for ebeam direct write (EBDW) lithography.

公开(公告)号：US20170076906A1

公开(公告)日：2017-03-16

申请号：US15122620

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Yan A. BORODOVSKY ,  Donald W. NELSON ,  Mark C. PHILLIPS

IPC: H01J37/04 ,  H01J37/317 ,  H01J37/20 ,  H01L21/027

CPC classification number: H01J37/3177 ,  H01J3/14 ,  H01J37/045 ,  H01J37/3026 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277 ,  H01L21/31144

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a blanker aperture array (BAA) for an e-beam tool includes a first column of openings along a first direction and having a pitch. The BAA also includes a second column of openings along the first direction and staggered from the first column of openings. The second column of openings has the pitch. A scan direction of the BAA is along a second direction, orthogonal to the first direction.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，用于电子束工具的消隐器孔径阵列（BAA）包括沿着第一方向的第一列开口并具有间距。 BAA还包括沿着第一方向的第二列开口并与第一列开口交错。 第二列开口具有间距。 BAA的扫描方向沿与第一方向垂直的第二方向。

公开(公告)号：US20170069509A1

公开(公告)日：2017-03-09

申请号：US15122398

申请日：2014-12-19

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Yan A. BORODOVSKY ,  Mark C. PHILLIPS ,  Robert M. BIGWOOD

IPC: H01L21/311 ,  H01J37/317 ,  H01J37/04 ,  H01L21/027 ,  H01J37/302

CPC classification number: H01L21/31144 ,  G03F7/2059 ,  G03F7/7045 ,  H01J37/045 ,  H01J37/3026 ,  H01J37/3174 ,  H01J37/3177 ,  H01J2237/0435 ,  H01J2237/0453 ,  H01J2237/303 ,  H01J2237/30422 ,  H01J2237/30438 ,  H01J2237/31762 ,  H01J2237/31764 ,  H01L21/0277

Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of data compression or data reduction for e-beam tool simplification involves providing an amount of data to write a column field and to adjust the column field for field edge placement error on a wafer, wherein the amount of data is limited to data for patterning approximately 10% or less of the column field. The method also involves performing e-beam writing on the wafer using the amount of data.

Abstract translation: 描述适用于涉及补充电子束光刻（CEBL）的光刻设备和方法。 在一个示例中，用于电子束工具简化的数据压缩或数据简化的方法包括提供一定量的数据来写入列字段并且调整用于晶片上的场边缘放置误差的列字段，其中数据量是 限于用于图案化的大约10％或更少的列场的数据。 该方法还涉及使用数据量在晶片上执行电子束写入。