公开(公告)号：US20240429294A1

公开(公告)日：2024-12-26

申请号：US18212824

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Makram ABD EL QADER ,  Ehren MANNEBACH

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

Abstract: Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.

公开(公告)号：US20240332302A1

公开(公告)日：2024-10-03

申请号：US18129874

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Debaleena NANDI ,  Ehren MANNEBACH ,  Shaun MILLS

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: Integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, and methods of fabricating integrated circuit structures having backside conductive source or drain contacts having enhanced contact area, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires or a fin. An epitaxial source or drain structure is laterally adjacent to and coupled to the vertical stack of horizontal nanowires or the fin. The epitaxial source or drain structure has a recess within a laterally surrounding outer portion. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is over and in contact with the epitaxial source or drain structure. The conductive source or drain contact is within the recess in the epitaxial source or drain structure.

公开(公告)号：US20230377947A1

公开(公告)日：2023-11-23

申请号：US18356780

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Aaron LILAK ,  Ehren MANNEBACH ,  Patrick MORROW ,  Anh PHAN ,  Willy RACHMADY ,  Hui Jae YOO

IPC: H01L21/762 ,  H01L21/225 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L21/266

CPC classification number: H01L21/76264 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26533 ,  H01L21/02236 ,  H01L21/02252 ,  H01L29/7853 ,  H01L29/0649 ,  H01L21/31111 ,  H01L21/76267 ,  H01L21/02255 ,  H01L21/266

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

公开(公告)号：US20220262796A1

公开(公告)日：2022-08-18

申请号：US17731110

申请日：2022-04-27

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20200212038A1

公开(公告)日：2020-07-02

申请号：US16236113

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Aaron LILAK ,  Brennen MUELLER ,  Hui Jae YOO ,  Patrick MORROW ,  Anh PHAN ,  Cheng-Ying HUANG ,  Ehren MANNEBACH ,  Kimin JUN ,  Gilbert DEWEY

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8238

Abstract: An integrated circuit structure comprises a substrate and a stacked channel of self-aligned heterogeneous materials, wherein the stacked channel of self-aligned heterogeneous materials comprises an NMOS channel material over the substrate; and a PMOS channel material stacked over and self-aligned with the NMOS channel material. A heterogeneous gate stack is in contact the both the NMOS channel material and the PMOS channel material.

公开(公告)号：US20240405085A1

公开(公告)日：2024-12-05

申请号：US18204204

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Patrick MORROW

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.

公开(公告)号：US20240332175A1

公开(公告)日：2024-10-03

申请号：US18129400

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Joseph D’SILVA ,  Ehren MANNEBACH ,  Mauro J. KOBRINSKY

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7869 ,  H01L29/78696

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming backside contacts on a transistor structure by forming, during front-side processing, trenches through the transistor structure into a silicon wafer, and then, using a catalytic oxidant material that is subsequently removed, forming an oxide structure in the silicon wafer around the trenches to isolate the backside gate contact from the source/drain trenches. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332172A1

公开(公告)日：2024-10-03

申请号：US18129872

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY ,  Makram ABD El QADER

IPC: H01L23/528 ,  H01L29/423

CPC classification number: H01L23/528 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.

公开(公告)号：US20240332077A1

公开(公告)日：2024-10-03

申请号：US18126851

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Shaun MILLS ,  Ehren MANNEBACH ,  Mauro J. KOBRINSKY

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/785

Abstract: Integrated circuit structures having backside gate connection are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive gate-to-contact connection is vertically beneath the epitaxial source or drain structure and vertically beneath and in electrical contact with the gate stack.

公开(公告)号：US20240332064A1

公开(公告)日：2024-10-03

申请号：US18126702

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Shaun MILLS ,  Joseph D’SILVA ,  Mauro J. KOBRINSKY

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L21/76808 ,  H01L21/76804 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.