公开(公告)号：US20230095402A1

公开(公告)日：2023-03-30

申请号：US17485190

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

公开(公告)号：US20220109025A1

公开(公告)日：2022-04-07

申请号：US17552546

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20200212105A1

公开(公告)日：2020-07-02

申请号：US16634109

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Elijah V. KARPOV ,  Ravi PILLARISETTY ,  Brian S. DOYLE

IPC: H01L27/24 ,  H01L27/22

Abstract: Embedded non-volatile memory structures having asymmetric selector elements are described. In an example, a memory device includes a word line. An asymmetric selector element is above the word line. The asymmetric selector element includes a first electrode material layer, a selector material layer on the first electrode material layer, and a second electrode material layer on the selector material layer, the second electrode material layer different in composition than the first electrode material layer. A bipolar memory element is above the word line, the bipolar memory element on the asymmetric selector element. A bit line is above the word line.

公开(公告)号：US20230360970A1

公开(公告)日：2023-11-09

申请号：US17738028

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Matthew METZ ,  Robert WILLONER

IPC: H01L21/768 ,  H01J37/32

CPC classification number: H01L21/76877 ,  H01J37/32009 ,  H01J2237/332 ,  H01J2237/08

Abstract: The present disclosure is directed to semiconductor deposition tools having a specimen support, at least one ion gun directed to a specimen positioned on the specimen support, at least one source, and at least one electron beam gun directed at the source. In an aspect, the electron beam guns, sources, and ion beam guns are positioned below the specimen support and specimen positioned thereon, which has its top surface facing downward. In another aspect, the method includes activating the electron beam gun and depositing the source material in a trench in the specimen and on surfaces adjacent to the opening of the trench and activating the ion beam gun to remove portions of the source material deposited on the surfaces adjacent to the opening of the trench.

公开(公告)号：US20230101212A1

公开(公告)日：2023-03-30

申请号：US17958295

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

公开(公告)号：US20200227477A1

公开(公告)日：2020-07-16

申请号：US16631156

申请日：2017-09-13

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20190229264A1

公开(公告)日：2019-07-25

申请号：US16320010

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Roza KOTLYAR ,  Prashant MAJHI ,  Jeffery D. BIELEFELD

IPC: H01L45/00

Abstract: Conductive bridge random access memory (CBRAM) devices with low thermal conductivity electrolyte sublayers are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes an active electrode layer disposed on the conductive interconnect, and a resistance switching layer disposed on the active electrode layer. The resistance switching layer includes a first electrolyte material layer disposed on a second electrolyte material layer, the second electrolyte material layer disposed on the active electrode layer and having a thermal conductivity lower than a thermal conductivity of the first electrolyte material layer. A passive electrode layer is disposed on the first electrolyte material of the resistance switching layer.

公开(公告)号：US20230116719A1

公开(公告)日：2023-04-13

申请号：US17485305

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11507 ,  H01L27/11514

Abstract: Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices with nitride-based ferroelectric materials. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220199801A1

公开(公告)日：2022-06-23

申请号：US17132996

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Brian S. DOYLE ,  Urusa ALAAN ,  Van H. LE ,  Elijah V. KARPOV ,  Kaan OGUZ ,  Arnab SEN GUPTA

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/683 ,  H01L29/78

Abstract: Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.

公开(公告)号：US20220199609A1

公开(公告)日：2022-06-23

申请号：US17133595

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Urusa ALAAN ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Benjamin ORR ,  Nicholas THOMSON ,  Ayan KAR ,  Arnab SEN GUPTA ,  Kaan OGUZ ,  Brian S. DOYLE ,  Prashant MAJHI ,  Van H. LE ,  Elijah V. KARPOV

IPC: H01L27/02 ,  H02H9/04

Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.