公开(公告)号：US20230187331A1

公开(公告)日：2023-06-15

申请号：US17549497

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Bainye Francoise ANGOUA ,  Chelsea GROVES ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Whitney BRYKS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49838 ,  H01L23/49866

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package that includes a glass core with one or more openings with one or more dies placed in the opening such that the glass core surrounds the one or more dies. One or one or more through glass via filled with conductive material such as copper electrically couple a first side of the glass core with a second side of the glass core opposite the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20190389179A1

公开(公告)日：2019-12-26

申请号：US16480593

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Praneeth AKKINEPALLY ,  Frank TRUONG ,  Dilan SENEVIRATNE

IPC: B32B15/08 ,  B32B27/36 ,  B32B15/20 ,  B32B7/12 ,  C09J7/40

Abstract: Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

公开(公告)号：US20210066447A1

公开(公告)日：2021-03-04

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Brandon C. MARIN ,  Jeremy ECTON ,  Hiroki TANAKA ,  Frank TRUONG

IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L21/48 ,  H01G4/28

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US20200083164A1

公开(公告)日：2020-03-12

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Frank TRUONG ,  Shivasubramanian BALASUBRAMANIAN ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sameer PAITAL ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Melissa WETTE ,  Srinivas PIETAMBARAM

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L23/00

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.