公开(公告)号：US20240014149A1

公开(公告)日：2024-01-11

申请号：US18372533

申请日：2023-09-25

申请人： Intel Corporation

发明人： Aleksandar ALEKSOV ,  Thomas SOUNART ,  Kristof DARMAWIKARTA ,  Henning BRAUNISCH ,  Prithwish CHATTERJEE ,  Andrew J. BROWN

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC分类号： H01L23/642 ,  H01L23/49894 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/49827 ,  H01L21/4846 ,  H01L2224/16265 ,  H01L2224/16225 ,  H01L2924/19103 ,  H01L2924/19041

摘要： Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US20200373157A1

公开(公告)日：2020-11-26

申请号：US16419426

申请日：2019-05-22

申请人： Intel Corporation

发明人： Jeremy D. ECTON ,  Brandon C. MARIN ,  Andrew J. BROWN ,  Dilan SENEVIRATNE

IPC分类号： H01L21/02 ,  H01L49/02 ,  H01L23/532 ,  H01L21/768

摘要： A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.

公开(公告)号：US20200006211A1

公开(公告)日：2020-01-02

申请号：US16019996

申请日：2018-06-27

申请人： INTEL CORPORATION

发明人： Andrew J. BROWN ,  Lauren A. LINK ,  Sai VADLAMANI ,  Prithwish CHATTERJEE ,  Lisa CHEN

IPC分类号： H01L23/498 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18 ,  H05K1/03 ,  D06M11/81 ,  D06B3/10 ,  D03D1/00 ,  D03D15/00 ,  B32B5/26 ,  B32B5/02 ,  B32B7/12

摘要： Apparatuses, systems and methods associated with substrate assemblies for computer devices are disclosed herein. In embodiments, a core for a substrate assembly includes a first metal region, a second metal region, and a dielectric region located between the first metal region and the second metal region. The dielectric region includes one or more fibers, wherein each of the one or more fibers includes aluminum, boron, silicon, or oxide. Other embodiments may be described and/or claimed.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

申请人： INTEL CORPORATION

发明人： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC分类号： H01L23/538 ,  H01L21/48

摘要： An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20210014972A1

公开(公告)日：2021-01-14

申请号：US16505403

申请日：2019-07-08

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

IPC分类号： H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

摘要： Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

公开(公告)号：US20200006005A1

公开(公告)日：2020-01-02

申请号：US16024715

申请日：2018-06-29

申请人： Intel Corporation

发明人： Rahul JAIN ,  Andrew J. BROWN ,  Prithwish CHATTERJEE ,  Sai VADLAMANI ,  Lauren LINK

IPC分类号： H01G4/33 ,  H01L49/02 ,  H01L23/522

摘要： Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.