公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

Applicant: Intel Corporation

Inventor： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20230146783A1

公开(公告)日：2023-05-11

申请号：US18089540

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Sri Ranga Sai Sai BOYAPATI

IPC: H01L23/532 ,  H01L23/29 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L23/293 ,  H01L23/5226 ,  H01L23/5385

Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

公开(公告)号：US20230146165A1

公开(公告)日：2023-05-11

申请号：US18091989

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Yonggang LI ,  Sameer PAITAL

IPC: H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64

CPC classification number: H01F27/26 ,  H01F27/425 ,  H01L21/76871 ,  H01L23/645 ,  H01F27/25

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US20230092242A1

公开(公告)日：2023-03-23

申请号：US17507010

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Gang DUAN

IPC: H01L23/15 ,  H01L21/768

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to a glass core within a substrate in a package, with one or more through glass vias (TGV) that are filled with a conductive material to electrically couple a first side of the glass core with a second side of the glass layer opposite the first side. A pad, also of conductive material, is electrically and physically coupled with a first and/or second end of the conductive material of the TGV. A layer of dielectric material is between at least a portion of the pad and the surface of the glass core between the pad and the glass core during manufacturing, handling, and/or operation to facilitate a reduction of stress cracks in the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20200373261A1

公开(公告)日：2020-11-26

申请号：US16421989

申请日：2019-05-24

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC: H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288

Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.

公开(公告)号：US20200328131A1

公开(公告)日：2020-10-15

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Roy DITTLER ,  Jeremy ECTON ,  Darko GRUJICIC

IPC: H01L23/31 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US20190279806A1

公开(公告)日：2019-09-12

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Sandeep GAAN ,  Sri Ranga Sai BOYAPATI ,  Prithwish CHATTERJEE ,  Sameer PAITAL ,  Rahul JAIN ,  Junnan ZHAO

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US20190206767A1

公开(公告)日：2019-07-04

申请号：US15859332

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Hiroki TANAKA ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Changhua LIU ,  Chung Kwang TAN ,  Srinivas PIETAMBARAM ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/485 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/027

CPC classification number: H01L23/485 ,  H01L21/0275 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/02 ,  H01L2223/54426 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/02372

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US20250125277A1

公开(公告)日：2025-04-17

申请号：US19000025

申请日：2024-12-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Sri Ranga Sai BOYAPATI ,  Robert A. MAY ,  Kristof DARMAWIKARTA ,  Javier SOTO GONZALEZ ,  Kwangmo LIM

IPC: H01L23/538 ,  H01L23/00

Abstract: A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.