公开(公告)号：US20240213301A1

公开(公告)日：2024-06-27

申请号：US18089471

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Thomas L. SOUNART ,  Benjamin DUONG ,  Kristof DARMAWIKARTA ,  Shayan KAVIANI ,  Suddhasattwa NAD ,  Mahdi MOHAMMADIGHALENI ,  Marcel WALL ,  Rengarajan SHANMUGAM

IPC: H01G4/33

CPC classification number: H01L28/40 ,  H01G4/33

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate that includes glass. In an embodiment, a cavity is provided into the core substrate. In an embodiment, a capacitor is lining sidewalls of the cavity, and the capacitor comprises a first layer, a dielectric layer over the first layer, and a second layer over the dielectric layer.

公开(公告)号：US20230091666A1

公开(公告)日：2023-03-23

申请号：US17482399

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Benjamin DUONG ,  Aleksandar ALEKSOV ,  Helme A. CASTRO DE LA TORRE ,  Kristof DARMAWIKARTA ,  Darko GRUJICIC ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Rengarajan SHANMUGAM ,  Thomas L. SOUNART ,  Marcel WALL

IPC: H05K1/18 ,  H05K1/03 ,  H01G4/33 ,  H05K1/11

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.

公开(公告)号：US20240188225A1

公开(公告)日：2024-06-06

申请号：US18060598

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Rengarajan SHANMUGAM ,  Srinivas PIETAMBARAM ,  Mao-Feng TSENG ,  Yonggang LI

IPC: H05K3/40 ,  C23C18/18 ,  C23C18/38 ,  H05K1/03 ,  H05K1/11 ,  H05K3/18

CPC classification number: H05K3/4038 ,  C23C18/1868 ,  C23C18/38 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/181 ,  H05K2201/09563 ,  H05K2201/2081 ,  H05K2203/107

Abstract: A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

公开(公告)号：US20220010452A1

公开(公告)日：2022-01-13

申请号：US17482513

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Chandrasekharan NAIR ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Srinivasan RAMAN ,  Roy DITTLER ,  Daniel SOWA ,  Robert BARESEL, II ,  Marcel WALL ,  Rahul MANEPALLI

IPC: C25D17/06 ,  C25D17/12 ,  C25D17/00 ,  H01L21/67

Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

公开(公告)号：US20250106997A1

公开(公告)日：2025-03-27

申请号：US18373088

申请日：2023-09-26

Applicant: Intel Corporation

Inventor： Ehsan ZAMANI ,  Umesh PRASAD ,  Logan MYERS ,  Shayan KAVIANI ,  Darko GRUJICIC ,  Elham TAVAKOLI ,  Mahdi MOHAMMADIGHALENI ,  Rengarajan SHANMUGAM ,  Rachel Guia GIRON ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN

IPC: H05K1/11 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a substrate that is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and a liner with a first surface is on a sidewall of the opening and a second surface is facing away from the sidewall of the opening. In an embodiment, the liner comprises a matrix, and filler particles in the matrix. In an embodiment, a plurality of cavities are provided into the second surface of the liner. In an embodiment, a via is in the opening, where the via is electrically conductive.

公开(公告)号：US20240332153A1

公开(公告)日：2024-10-03

申请号：US18129880

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Tchefor NDUKUM ,  Yonggang LI ,  Rengarajan SHANMUGAM ,  Darko GRUJICIC ,  Deniz TURAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

公开(公告)号：US20210090946A1

公开(公告)日：2021-03-25

申请号：US16578698

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Matthew ANDERSON ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Benjamin DUONG ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI ,  Suddhasattwa NAD ,  Rengarajan SHANMUGAM ,  Marcel WALL

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

公开(公告)号：US20200258975A1

公开(公告)日：2020-08-13

申请号：US16271639

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Rengarajan SHANMUGAM ,  Suddhasattwa NAD ,  Darko GRUJICIC ,  Srinivas PIETAMBARAM

IPC: H01L49/02 ,  H01L23/498 ,  H01L23/66 ,  H01F27/28 ,  H01F27/24 ,  H01L25/16 ,  H01L23/552 ,  H01L21/48 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

公开(公告)号：US20200245472A1

公开(公告)日：2020-07-30

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Sandeep GAAN ,  Adrian BAYRAKTAROGLU ,  Roy DITTLER ,  Ke LIU ,  Suddhasattwa NAD ,  Marcel A. WALL ,  Rahul N. MANEPALLI ,  Ravindra V. TANIKELLA

IPC: H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01L21/48 ,  C23C18/16 ,  C23C18/18 ,  C23C18/38

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US20200083164A1

公开(公告)日：2020-03-12

申请号：US16129711

申请日：2018-09-12

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Frank TRUONG ,  Shivasubramanian BALASUBRAMANIAN ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sameer PAITAL ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Melissa WETTE ,  Srinivas PIETAMBARAM

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L23/00

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.