公开(公告)号：US20240112951A1

公开(公告)日：2024-04-04

申请号：US17957721

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Philip Yashar ,  Gokul Malyavanatham ,  Hema Vijwani

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76843 ,  H01L21/76867 ,  H01L23/49894

Abstract: Integrated circuit interconnect structures including a niobium-based barrier material. In some embodiments, a layer of essentially niobium may be sputter deposited, for example to a thickness of less than 8 nm at a bottom of an interconnect via. A copper-based fill material may then be deposited over the niobium barrier material. Integrated circuit interconnect metallization may comprise some layers of metallization that have a tantalum-based barrier and other layers of metallization that have a niobium-based barrier.

公开(公告)号：US11430944B2

公开(公告)日：2022-08-30

申请号：US16358671

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Christopher Wiegand ,  Gokul Malyavanatham ,  Oleg Golonzka

IPC: H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L45/00 ,  H01L43/12

Abstract: An apparatus includes a first interconnect structure above a substrate, a memory device above and coupled with the first interconnect structure in a memory region. The memory device includes a non-volatile memory element, an electrode on the non-volatile memory element, and a metallization structure on a portion of the electrode. The apparatus further includes a second interconnect structure in a logic region above the substrate, where the second interconnect structure is laterally distant from the first interconnect structure. The logic region further includes a second metallization structure coupled to the second interconnect structure and a conductive structure between the second metallization structure and the second interconnect structure. The apparatus further includes a dielectric spacer that extends from the memory device to the conductive structure.

公开(公告)号：US20190304918A1

公开(公告)日：2019-10-03

申请号：US15937527

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US11270943B2

公开(公告)日：2022-03-08

申请号：US15937527

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US10446439B2

公开(公告)日：2019-10-15

申请号：US15769432

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Philip Yashar ,  Gokul Malyavanatham

IPC: H01L21/285 ,  H01L23/532 ,  H01L21/768

Abstract: An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.

公开(公告)号：US20180301373A1

公开(公告)日：2018-10-18

申请号：US15769432

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Philip Yashar ,  Gokul Malyavanatham

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53238

Abstract: An embodiment includes a transmitter comprising: an oxide layer between a substrate and an epitaxial silicon layer; a modulator included within the silicon layer and a hybrid laser on the silicon layer; wherein (a) the silicon layer is thinner directly adjacent the modulator than directly adjacent the laser; and (b) the silicon layer comprises gratings directly under the laser and directly contacting the oxide layer. Other embodiments are described herein.