公开(公告)号：US10777421B2

公开(公告)日：2020-09-15

申请号：US15706992

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Jason A. Farmer ,  Gopinath Trichy ,  Justin S. Sandford ,  Daniel B. Bergstrom

IPC: H01L21/311 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L21/324 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. Microelectronic devices including first and second fins that are laterally offset by a fin pitch to define a first field there between are also described. In embodiments the microelectronic devices include a conformal oxide layer and a conformal nitride layer on at least a portion of the first and second fins, where the conformal nitride layer is on at least a portion of the conformal oxide layer and a sacrificial oxide material is disposed within the first field.

公开(公告)号：US20190304918A1

公开(公告)日：2019-10-03

申请号：US15937527

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US11270943B2

公开(公告)日：2022-03-08

申请号：US15937527

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US20180005841A1

公开(公告)日：2018-01-04

申请号：US15706992

申请日：2017-09-18

Applicant: Intel Corporation

Inventor： Jason A. Farmer ,  Gopinath Trichy ,  Justin S. Sandford ,  Daniel B. Bergstrom

IPC: H01L21/311 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L21/31116 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: Technologies for selectively etching oxide and nitride materials on a work piece are described. Such technologies include methods for etching a work piece with a remote plasma that is produced by igniting a plasma gas flow. By controlling the flow rate of various components of the plasma gas flow, plasmas exhibiting desired etching characteristics may be obtained. Such plasmas may be used in single or multistep etching operations, such as recess etching operations that may be used in the production of non-planar microelectronic devices.