公开(公告)号：US10468298B2

公开(公告)日：2019-11-05

申请号：US16249593

申请日：2019-01-16

申请人： Intel Corporation

发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/532 ,  H01L23/528

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US11749560B2

公开(公告)日：2023-09-05

申请号：US16141522

申请日：2018-09-25

申请人： INTEL CORPORATION

发明人： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC分类号： H01L21/768 ,  H01L23/532 ,  C25D3/58 ,  C23C18/48

CPC分类号： H01L21/76802 ,  C23C18/48 ,  C25D3/58 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53223 ,  H01L23/53238

摘要： Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US10903114B2

公开(公告)日：2021-01-26

申请号：US16582923

申请日：2019-09-25

申请人： Intel Corporation

发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/528

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US20200098619A1

公开(公告)日：2020-03-26

申请号：US16141522

申请日：2018-09-25

申请人： INTEL CORPORATION

发明人： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC分类号： H01L21/768 ,  H01L23/532 ,  C23C18/48 ,  C25D3/58

摘要： Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US20190304918A1

公开(公告)日：2019-10-03

申请号：US15937527

申请日：2018-03-27

申请人： INTEL CORPORATION

发明人： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

摘要： An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

公开(公告)号：US11018054B2

公开(公告)日：2021-05-25

申请号：US16486612

申请日：2017-04-12

申请人： Intel Corporation

发明人： Daniel J. Zierath ,  Flavio Griggio ,  John D. Brooks

IPC分类号： H01L21/76 ,  H01L27/06 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532

摘要： Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.

公开(公告)号：US20200013673A1

公开(公告)日：2020-01-09

申请号：US16486612

申请日：2017-04-12

申请人： Intel Corporation

发明人： Daniel J. Zierath ,  Flavio Griggio ,  John D. Brooks

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/321 ,  H01L27/06

摘要： Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.

公开(公告)号：US10211098B2

公开(公告)日：2019-02-19

申请号：US16005175

申请日：2018-06-11

申请人： INTEL CORPORATION

发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/532

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US11652067B2

公开(公告)日：2023-05-16

申请号：US16465126

申请日：2016-12-28

申请人： Intel Corporation

发明人： Christopher J. Jezewski ,  Radek P. Chalupa ,  Flavio Griggio ,  Inane Meric ,  Jiun-Chan Yang

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/562 ,  H01L21/7684 ,  H01L23/5226

摘要： Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.

公开(公告)号：US11270943B2

公开(公告)日：2022-03-08

申请号：US15937527

申请日：2018-03-27

申请人： INTEL CORPORATION

发明人： Flavio Griggio ,  Philip Yashar ,  Anthony V. Mule ,  Gopinath Trichy ,  Gokul Malyavanatham

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

摘要： An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.