公开(公告)号：US20170019350A1

公开(公告)日：2017-01-19

申请号：US14800552

申请日：2015-07-15

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Chung-Chi Wang ,  Donald C. Soltis, JR. ,  Terry C. Huang ,  Tejpal Singh ,  Bongjin Jung ,  Nazar Syed Haider

IPC: H04L12/933 ,  H04L12/937

CPC classification number: H04L49/103 ,  G06F11/1064 ,  G06F13/4022 ,  H04L49/254

Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

Abstract translation: 共享网格包括网格站。 网状站用于耦合到至少第一核心组件和第二核心组件。 网格站包括一个逻辑单元。 网状站由至少第一核心组件和第二核心组件共享。 存储器耦合到网格站。

公开(公告)号：US20150160720A1

公开(公告)日：2015-06-11

申请号：US14519584

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： James R. Vash ,  Pritpal S. Ahuja ,  Bongjin Jung ,  Jeffrey D. Chamberlain

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F13/00 ,  G06F13/1642 ,  H04L29/00 ,  Y02D10/14

Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。 在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。 此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。 还公开了其他实施例。

公开(公告)号：US10193826B2

公开(公告)日：2019-01-29

申请号：US14800552

申请日：2015-07-15

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Chung-Chi Wang ,  Donald C. Soltis, Jr. ,  Terry C. Huang ,  Tejpal Singh ,  Bongjin Jung ,  Nazar Syed Haider

IPC: H04L12/933 ,  H04L12/937 ,  G06F13/40 ,  G06F11/10

Abstract: A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

公开(公告)号：US20160077970A1

公开(公告)日：2016-03-17

申请号：US14484642

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Aamer Jaleel ,  Bongjin Jung ,  Zeshan A. Chishti ,  Adrian C. Moga ,  Eric Delano ,  Ren Wang

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/1024

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

Abstract translation: 根据本文公开的实施例，提供了用于提供虚拟共享高速缓存机制的系统和方法。 处理设备包括分配到虚拟专用共享高速缓存中的多个群集。 每个群集包括多个核和多个高速缓存片，共同定位在多个核中。 处理装置还包括包含多个群集的虚拟共享高速缓存，使得多个高速缓存片段中的高速缓存数据在多个群集之间共享。

公开(公告)号：US11916800B2

公开(公告)日：2024-02-27

申请号：US16912553

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： David Arditti Ilitzky ,  John Greth ,  Robert Southworth ,  Karl S. Papadantonakis ,  Bongjin Jung ,  Arvind Srinivasan

IPC: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L49/00 ,  H04L47/125 ,  H04L49/25 ,  H04L49/90 ,  H04L47/62

CPC classification number: H04L47/283 ,  H04L43/087 ,  H04L43/16 ,  H04L47/125 ,  H04L47/6205 ,  H04L49/25 ,  H04L49/3063 ,  H04L49/9042

Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.

公开(公告)号：US11722438B2

公开(公告)日：2023-08-08

申请号：US16546993

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John Greth ,  Arvind Srinivasan ,  Robert Southworth ,  David Arditti Ilitzky ,  Bongjin Jung ,  Gaspar Mora Porta

IPC: H04L49/00 ,  H04L49/25 ,  H04L9/40 ,  H04L69/22 ,  H04L41/0896 ,  H04L49/90

CPC classification number: H04L49/3045 ,  H04L41/0896 ,  H04L49/257 ,  H04L49/9042 ,  H04L63/101 ,  H04L69/22

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

公开(公告)号：US09792212B2

公开(公告)日：2017-10-17

申请号：US14484642

申请日：2014-09-12

Applicant: Intel Corporation

Inventor： Yen-Cheng Liu ,  Aamer Jaleel ,  Bongjin Jung ,  Zeshan A. Chishti ,  Adrian C. Moga ,  Eric Delano ,  Ren Wang

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0831

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/0846 ,  G06F2212/1024

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

公开(公告)号：US09207753B2

公开(公告)日：2015-12-08

申请号：US14519584

申请日：2014-10-21

Applicant: Intel Corporation

Inventor： James R. Vash ,  Pritpal S. Ahuja ,  Bongjin Jung ,  Jeffrey D. Chamberlain

IPC: G06F1/32 ,  G06F13/00 ,  G06F13/16 ,  H04L29/00

CPC classification number: G06F1/3293 ,  G06F13/00 ,  G06F13/1642 ,  H04L29/00 ,  Y02D10/14

Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。 在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。 此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。 还公开了其他实施例。

公开(公告)号：US09304922B2

公开(公告)日：2016-04-05

申请号：US14307019

申请日：2014-06-17

Applicant: Intel Corporation

Inventor： James R. Vash ,  Bongjin Jung ,  Pritpal S. Ahuja

IPC: G06F13/38 ,  G06F12/08 ,  G06F13/16 ,  G06F13/00

CPC classification number: G06F12/0815 ,  G06F13/1642 ,  G06F2212/621

Abstract: Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.

Abstract translation: 描述了在基于重试的管道中与具有动态死锁避免的队列间抗饥饿机制有关的方法和装置。 在一个实施例中，逻辑可以基于各种规则在两个队列之间仲裁。 队列可以存储包括本地或远程请求，数据响应，非数据响应，外部中断等的数据。还公开了其他实施例。

公开(公告)号：US09288260B2

公开(公告)日：2016-03-15

申请号：US14048254

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

IPC: G06F15/16 ,  H04L29/08 ,  G06F15/173

CPC classification number: H04L67/10 ,  G06F15/17325

Abstract: Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.