公开(公告)号：US20160034224A1

公开(公告)日：2016-02-04

申请号：US14815508

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与非易失性存储器上的数据结构的瞬态和持久状态之间就地改变相关的方法和装置。 在一个实施例中，控制器逻辑引起一个或多个非易失性存储器件的第一部分在持久状态和瞬态之间的状态的改变，而不移动存储在一个或多个非易失性存储器件的第一部分中的数据 存储设备。 还公开并要求保护其他实施例。

公开(公告)号：US09335944B2

公开(公告)日：2016-05-10

申请号：US14815508

申请日：2015-07-31

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/50 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

公开(公告)号：US09128824B2

公开(公告)日：2015-09-08

申请号：US13726303

申请日：2012-12-24

Applicant: Intel Corporation

Inventor： Matthias Gries ,  Marcelo Cintra ,  Thomas Lehnig ,  Sebastian Steibl ,  Tor Lund-Larsen

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/50

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0643 ,  G06F3/0679 ,  G06F9/5061 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  Y02D10/13

Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与非易失性存储器上的数据结构的瞬态和持久状态之间就地改变相关的方法和装置。 在一个实施例中，控制器逻辑引起一个或多个非易失性存储器件的第一部分在持久状态和瞬态之间的状态的改变，而不移动存储在一个或多个非易失性存储器件的第一部分中的数据 存储设备。 还公开并要求保护其他实施例。

公开(公告)号：US09645938B2

公开(公告)日：2017-05-09

申请号：US14127483

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Tim Kranich ,  Matthias Gries ,  Niklas Linkewitsch

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0846 ,  G06F9/44 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/12 ,  G06F12/0802 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F9/4406 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0848 ,  G06F12/0877 ,  G06F12/0893 ,  G06F12/1054 ,  G06F12/12 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/60 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7211 ,  Y02D10/13

Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.