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    Liner for phase change memory (PCM) array and associated techniques and configurations
    1.
    发明授权
    Liner for phase change memory (PCM) array and associated techniques and configurations 有权
    相变存储器（PCM）阵列和相关技术和配置的衬垫

    公开(公告)号：US09397143B2

    公开(公告)日：2016-07-19

    申请号：US14137864

    申请日：2013-12-20

    Applicant: INTEL CORPORATION

    Inventor： Noel Rocklein ,  Qian Tao ,  Zhe Song ,  Vishwanath Bhat

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1675

    Abstract: Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a substrate, an array of phase change memory (PCM) elements disposed on the substrate, wherein individual PCM elements of the array of PCM elements comprise a chalcogenide material and a liner disposed on sidewall surfaces of the individual PCM elements, wherein the liner comprises aluminum (Al), silicon (Si) and oxygen (O). Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了用于相变存储器（PCM）阵列和相关联的技术和配置的衬垫。 在一个实施例中，衬底，设置在衬底上的相变存储器（PCM）元件的阵列，其中PCM元件阵列的各个PCM元件包括硫族化物材料和设置在各个PCM元件的侧壁表面上的衬垫，其中 衬垫包括铝（Al），硅（Si）和氧（O）。 可以描述和/或要求保护其他实施例。

    3D NAND with integral drain-end select gate (SGD)
    2.
    发明授权
    3D NAND with integral drain-end select gate (SGD) 有权

    公开(公告)号：US10790290B2

    公开(公告)日：2020-09-29

    申请号：US15721224

    申请日：2017-09-29

    Applicant: INTEL CORPORATION

    Inventor： David A. Daycock ,  Purnima Narayanan ,  John Hopkins ,  Guoxing Duan ,  Barbara L. Casey ,  Christopher J. Larsen ,  Meng-Wei Kuo ,  Qian Tao

    IPC: H01L27/11524 ,  H01L27/1157 ,  H01L21/8234 ,  H01L27/11582 ,  H01L27/11556

    Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

    COMPUTER MEMORY
    4.
    发明申请
    COMPUTER MEMORY 审中-公开

    公开(公告)号：US20190005996A1

    公开(公告)日：2019-01-03

    申请号：US15640530

    申请日：2017-07-01

    Applicant: Intel Corporation

    Inventor： Christopher J. Larsen ,  David A. Daycock ,  Qian Tao ,  Saniya Rathod ,  Devesh K. Datta ,  Srivardhan Gowda ,  Rithu K. Bhonsle

    IPC: G11C8/12 ,  G11C5/02 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C19/28

    Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

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