公开(公告)号：US10318170B2

公开(公告)日：2019-06-11

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US09857989B1

公开(公告)日：2018-01-02

申请号：US15283296

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.

公开(公告)号：US11010058B2

公开(公告)日：2021-05-18

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damaria ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US10790290B2

公开(公告)日：2020-09-29

申请号：US15721224

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： David A. Daycock ,  Purnima Narayanan ,  John Hopkins ,  Guoxing Duan ,  Barbara L. Casey ,  Christopher J. Larsen ,  Meng-Wei Kuo ,  Qian Tao

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L21/8234 ,  H01L27/11582 ,  H01L27/11556

Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.

公开(公告)号：US10762939B2

公开(公告)日：2020-09-01

申请号：US15640530

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Qian Tao ,  Saniya Rathod ,  Devesh K. Datta ,  Srivardhan Gowda ,  Rithu K. Bhonsle

IPC: G11C11/34 ,  G11C8/12 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C19/28 ,  H01L27/11582 ,  G11C5/02 ,  G11C16/04

Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

公开(公告)号：US20190005996A1

公开(公告)日：2019-01-03

申请号：US15640530

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Christopher J. Larsen ,  David A. Daycock ,  Qian Tao ,  Saniya Rathod ,  Devesh K. Datta ,  Srivardhan Gowda ,  Rithu K. Bhonsle

IPC: G11C8/12 ,  G11C5/02 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C19/28

Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

公开(公告)号：US20180307412A1

公开(公告)日：2018-10-25

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20190294330A1

公开(公告)日：2019-09-26

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.