公开(公告)号：US20230350687A1

公开(公告)日：2023-11-02

申请号：US18143513

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

CPC classification number: G06F9/3842 ,  G06F9/30145 ,  G06F21/556 ,  G06F9/30058 ,  G06F2221/033

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20190324756A1

公开(公告)日：2019-10-24

申请号：US16236049

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： ROBERT S. CHAPPELL ,  JASON W. BRANDT ,  ALAN COX ,  ASIT MALLICK ,  JOSEPH NUZMAN ,  ARJAN VAN DE VEN

IPC: G06F9/38 ,  G06F9/30 ,  G06F21/55

Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.

公开(公告)号：US20200310978A1

公开(公告)日：2020-10-01

申请号：US16367103

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： SCOTT DION RODGERS ,  ROBERT S. CHAPPELL ,  BARRY E. HUNTLEY

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method for managing different page tables for different privilege levels. For example, one embodiment of a processor comprises: a first control register to store a first base address associated with program code executed at a first privilege level; a second control register to store a second base address associated with program code executed at a second privilege level lower than the first privilege level; and address translation circuitry to identify a first base translation table using the first base address responsive to a first address translation request originating from the program code executed at the first privilege level and to identify a second base translation table using the second base address responsive to a second address translation request originating from the program code executed at the second privilege level.

公开(公告)号：US20180225228A1

公开(公告)日：2018-08-09

申请号：US15883021

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： ROBERT S. CHAPPELL ,  JOHN W. FAISTL ,  HERMANN W. GARTLER ,  MICHAEL D. TUCKNOTT ,  RAJESH S. PARTHASARATHY ,  DAVID W. BURNS

IPC: G06F12/14 ,  G06F12/0862

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

公开(公告)号：US20170097902A1

公开(公告)日：2017-04-06

申请号：US15384203

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： ROBERT S. CHAPPELL ,  JOHN W. FAISTL ,  HERMANN W. GARTLER ,  MICHAEL D. TUCKNOTT ,  RAJESH S. PARTHASARATHY ,  DAVID W. BURNS

IPC: G06F12/14 ,  G06F12/0862

CPC classification number: G06F12/1491 ,  G06F9/52 ,  G06F9/526 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/126 ,  G06F12/1466 ,  G06F13/42 ,  G06F2212/1052 ,  G06F2212/602

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.