公开(公告)号：US20180240874A1

公开(公告)日：2018-08-23

申请号：US15754150

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： CORY E. WEBER ,  SAURABH MORARKA ,  RITESH JHAVERI ,  GLENN A. GLASS ,  SZUYA S. LIAO ,  ANAND S. MURTHY

IPC: H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/30612 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.