公开(公告)号：US20180240874A1

公开(公告)日：2018-08-23

申请号：US15754150

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： CORY E. WEBER ,  SAURABH MORARKA ,  RITESH JHAVERI ,  GLENN A. GLASS ,  SZUYA S. LIAO ,  ANAND S. MURTHY

IPC: H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/30612 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

公开(公告)号：US20190355721A1

公开(公告)日：2019-11-21

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  SCOTT J. MADDOX ,  RITESH JHAVERI ,  PRATIK A. PATEL ,  SZUYA S. LIAO ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US20190207015A1

公开(公告)日：2019-07-04

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  CORY E. WEBER ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  JIONG ZHANG ,  RITESH JHAVERI ,  SZUYA S. LIAO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.