公开(公告)号：US11094370B2

公开(公告)日：2021-08-17

申请号：US16728679

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Shadi T. Khasawneh ,  Mukund Ramakrishna

IPC: G06F13/28 ,  G11C11/4094 ,  G11C11/4076 ,  G11C11/4093 ,  G06F12/12 ,  G11C11/4091 ,  G11C11/408 ,  G11C13/00

Abstract: Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row.

公开(公告)号：US09418024B2

公开(公告)日：2016-08-16

申请号：US14039424

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Ahmad A. Samih ,  Shadi T. Khasawneh

IPC: G06F12/00 ,  G06F13/16 ,  G06F12/08 ,  G06F9/46

CPC classification number: G06F13/16 ,  G06F9/46 ,  G06F12/0859 ,  Y02D10/13

Abstract: An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a respective plurality of data processing functions, at least one of the data processing functions comprising transmitting and receiving chunks of data to and from a memory controller, respectively; a system agent to coordinate requests for transmitting and receiving the chunks of data to and from the memory controller, the system agent comprising: a memory for temporarily storing the chunks of data during transmission between the agents and the memory controller; and scheduling logic to prioritize critical chunks over non-critical chunks across multiple outstanding requests while ensuring that the non-critical chunks do not result in starvation.

Abstract translation: 一种有效处理关键块的装置和方法。 例如，设备的一个实施例包括多个代理以执行相应的多个数据处理功能，所述数据处理功能中的至少一个分别包括向存储器控制器发送数据块和从存储器控制器接收数据块; 系统代理，用于协调向存储器控制器发送和接收数据块的请求，所述系统代理包括：存储器，用于在代理和存储器控制器之间的传输期间临时存储数据块; 以及调度逻辑，以跨多个未完成请求优先处理非关键块的关键块，同时确保非关键块不会导致缺陷。

公开(公告)号：US09767026B2

公开(公告)日：2017-09-19

申请号：US13997437

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Jose S. Niell ,  Daniel F. Cutter ,  James D. Allen ,  Deepak Limaye ,  Shadi T. Khasawneh

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1027

CPC classification number: G06F12/0831 ,  G06F12/1027 ,  Y02D10/13

Abstract: In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip (SoC). The conflict detection logic includes snoop filter logic to downgrade a first snooped memory request for a first address to an unsnooped memory request when an indicator associated with the first address indicates that the coherent fabric has control of the first address. Other embodiments are described and claimed.