公开(公告)号：US10859627B2

公开(公告)日：2020-12-08

申请号：US15636762

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC: G01R31/317 ,  H04L12/26 ,  G01R31/26 ,  H04L12/24 ,  G01R31/28

Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC: H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.

公开(公告)号：US09654143B2

公开(公告)日：2017-05-16

申请号：US14308107

申请日：2014-06-18

Applicant: Intel Corporation

Inventor： Guillem Sole ,  Roger Espasa ,  Sorin Iacobovici ,  Brian Hickmann ,  Wei Wu ,  Thomas Fletcher

IPC: G06F11/10 ,  H03M13/09 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

CPC classification number: H03M13/09 ,  G06F11/1012 ,  H03M13/17 ,  H03M13/19 ,  H03M13/29

Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

公开(公告)号：US09110768B2

公开(公告)日：2015-08-18

申请号：US13730008

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Sorin Iacobovici

IPC: G06F11/10 ,  G06F7/72

CPC classification number: G06F7/72 ,  G06F7/483 ,  G06F11/085

Abstract: An error detection unit including one or more register files that store at least one operand and at least one operand residue, an operand multiplexor operable to receive the operand, a residue multiplexor operable to receive the operand residue, a source operand residue generator operable to generate at least one generated residue from the operand, a first comparator that compares the operand residue to the generated residue, the result of the first comparator being sent to a reorder buffer, an execution unit that supplies the operand to a residue calculator and a result residue generator, wherein the residue calculator operable to determine an expected residue and the result residue generator operable to generate a result residue, and a second comparator that compares the expected residue with the result residue, the result of the second comparator being sent to the reorder buffer.

Abstract translation: 一种错误检测单元，包括存储至少一个操作数和至少一个操作数残差的一个或多个寄存器文件，可操作以接收操作数的操作数多路复用器，可操作以接收操作数残差的残余多路复用器，可操作以产生 来自操作数的至少一个产生的残差，将操作数残差与所生成的残差进行比较的第一比较器，将第一比较器的结果发送到重排序缓冲器，将操作数提供给残差计算器的执行单元和结果残差 发生器，其中所述残差计算器可操作以确定预期残留，并且所述结果残留发生器可操作以产生结果残留;以及第二比较器，将所述预期残差与所述结果残差进行比较，所述第二比较器的结果被发送到所述重排序缓冲器 。