公开(公告)号：US11257560B2

公开(公告)日：2022-02-22

申请号：US15717721

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Fei Su ,  Puneet Gupta ,  Wei Ming Lim ,  Terrence Huat Hin Tan ,  Amit Sanghani ,  Anubhav Sinha ,  Sudheer V Badana ,  Rakesh Kandula ,  Adithya B. S.

IPC: G11C29/12 ,  G11C29/48 ,  H01L23/538 ,  H03K17/56 ,  H03K17/00 ,  G11C29/50 ,  G11C29/02 ,  H01L25/065 ,  H01L23/00

Abstract: A die-to-die repeater circuit includes a transmit circuit coupled to a die-to-die interconnect, the transmit circuit including at least one flip flop to function as a part of a linear feedback shift register (LFSR) to transmit a value across the die-to-die interconnect for design for test (DFT) to check proper operation of the die-to-die interconnect, and a receive circuit coupled to the die-to-die interconnect, the receive circuit including at least one flip flop to function as part of a multiple input shift register (MISR).

公开(公告)号：US20190051370A1

公开(公告)日：2019-02-14

申请号：US16155606

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Asad Azam ,  R Selvakumar Raja Gopal ,  Sreejit Chakravarty ,  Kaitlyn Chen

IPC: G11C29/42 ,  G11C29/36

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

公开(公告)号：US11335428B2

公开(公告)日：2022-05-17

申请号：US16155606

申请日：2018-10-09

Applicant: Intel Corporation

Inventor： Asad Azam ,  R Selvakumar Raja Gopal ,  Sreejit Chakravarty ,  Kaitlyn Chen

IPC: G11C29/42 ,  G11C29/36 ,  G11C29/04 ,  G01R31/3177 ,  G06F11/16 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3181 ,  G06F11/263 ,  G06F30/333 ,  G01R31/3185

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

公开(公告)号：US10859627B2

公开(公告)日：2020-12-08

申请号：US15636762

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC: G01R31/317 ,  H04L12/26 ,  G01R31/26 ,  H04L12/24 ,  G01R31/28

Abstract: A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC: H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

Abstract: A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.