公开(公告)号：US20230102991A1

公开(公告)日：2023-03-30

申请号：US17484542

申请日：2021-09-24

申请人： Intel Corporation

发明人： Michael Mishaeli ,  Edward Brazil ,  Bryan J. Gran ,  Ohad Itzhaki

IPC分类号： G06F11/22 ,  G06F11/273 ,  G06F11/263

摘要： Systems, methods, and apparatuses for autonomous functional testing of a processor are described. In one example, a processor includes a plurality of processor cores that are each coupled to a respective power management agent circuit; a cache shared by the plurality of processor cores; and a control register, that when set, causes: a save of a state of a first processor core of the plurality of processor cores to storage, a transfer of control of the first processor core to a power management agent circuit of the first processor core, isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, performance of one or more functional tests from the cache on the first processor core caused by the power management agent circuit to generate a test result, removal of the isolation of the first processor core from the other of the plurality of processor cores by the power management agent circuit, and a transfer of the control by the power management agent circuit back to the first processor core.

公开(公告)号：US10859627B2

公开(公告)日：2020-12-08

申请号：US15636762

申请日：2017-06-29

申请人： Intel Corporation

发明人： Sreejit Chakravarty ,  Oscar Mendoza ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici ,  Neel Shah ,  Michael Neve de Mevergnies ,  John Cruz Mejia ,  Amy L. Santoni

IPC分类号： G01R31/317 ,  H04L12/26 ,  G01R31/26 ,  H04L12/24 ,  G01R31/28

摘要： A processor, including: a core; system test circuitry, the system test circuitry to be locked during operational processor operation; reset circuitry including a kick-off test (KOT) input, the reset circuitry to detect a reset with the KOT input asserted, and to initiate an in-field system test (IFST) mode; a test interface controller to receive in IFST mode an encrypted test packet having a signature, verify the signature of the test packet, and decrypt the test packet; and IFST control circuitry to cause the system test circuitry to perform an IFST test according to the decrypted test packet and to log or report results.

公开(公告)号：US20190007200A1

公开(公告)日：2019-01-03

申请号：US15638162

申请日：2017-06-29

申请人： INTEL CORPORATION

发明人： Neel Shah ,  Kirk S. Yap ,  Amy L. Santoni ,  Michael Neve de Mevergnies ,  Oscar Mendoza ,  Sreejit Chakravarty ,  Ramasubramanian Rajamani ,  Bryan J. Gran ,  Sorin Iacobovici

IPC分类号： H04L9/08 ,  G01R31/317 ,  G01R31/26 ,  H04L9/06

摘要： A processor, including: a core; system test circuitry, the system test circuitry configured to be locked except during an in-field system test (IFST) mode; IFST control circuitry; and a test interface controller, including: a data interface to receive a test packet; a parser to parse the test packet into a key, a signature, and a stored hash-of-hashes; a decryption circuit to decrypt the signature according to the key and to generate a computed hash-of-hashes; a hash circuit to verify the stored hash-of-hashes against the computed hash-of-hashes; and an IFST interface, wherein the test interface controller is to signal the IFST control circuitry to place the system test circuitry in IFST mode.