公开(公告)号：US20170263551A1

公开(公告)日：2017-09-14

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  MANISH CHANDHOK ,  JASMEET S. CHAWLA ,  FLORIAN GSTREIN ,  EUNGNAK HAN ,  RAMI HOURANI ,  KEVIN LIN ,  RICHARD E. SCHENKER ,  TODD R. YOUNKIN

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1026

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US20170263496A1

公开(公告)日：2017-09-14

申请号：US15529479

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MICHAEL J. LEESON ,  TODD R. YOUNKIN ,  EUNGNAK HAN ,  ROBERT L. BRISTOL

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/165 ,  H01L21/0271 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.