公开(公告)号：US20160197011A1

公开(公告)日：2016-07-07

申请号：US14912036

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  FLORIAN GSTREIN ,  RICHARD E. SCHENKER ,  PAUL A. NYHUS ,  CHARLES H. WALLACE ,  HUI JAE YOO

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

Abstract translation: 描述了用于后端（BEOL）互连的消减自对准通孔和插塞图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 互连结构还包括设置在互连结构的第一层上方的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有低于金属线的最下表面的最下表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一光栅的金属线与第二光栅的金属线间隔开。

公开(公告)号：US20170263553A1

公开(公告)日：2017-09-14

申请号：US15529484

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RICHARD E. SCHENKER ,  MANISH CHANDHOK ,  ROBERT L. BRISTOL ,  MAURO J. KOBRINSKY ,  KEVIN LIN

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5283 ,  H01L23/53295

Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.

公开(公告)号：US20170263551A1

公开(公告)日：2017-09-14

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  MANISH CHANDHOK ,  JASMEET S. CHAWLA ,  FLORIAN GSTREIN ,  EUNGNAK HAN ,  RAMI HOURANI ,  KEVIN LIN ,  RICHARD E. SCHENKER ,  TODD R. YOUNKIN

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1026

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US20150253667A1

公开(公告)日：2015-09-10

申请号：US14642328

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： ROBERT L. BRISTOL ,  PAUL A. NYHUS ,  CHARLES H. WALLACE

IPC: G03F7/095 ,  H01L21/033 ,  H01L21/027

CPC classification number: G03F7/095 ,  G03F7/0002 ,  G03F7/0035 ,  G03F7/0043 ,  G03F7/0045 ,  G03F7/094 ,  G03F7/2037 ,  G03F7/2039 ,  G03F7/2041 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/0334 ,  Y10S430/143 ,  Y10S430/168 ,  Y10T428/24851

Abstract: A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a dose of 10.0 mJ/cm2 or greater and removing a portion of said the and forming guiding features. The method also includes etching the hardmask to form isolating features in the hardmask, applying a second resist within the isolating features forming regions of the second resist in the hardmask, and exposing regions of the second resist to electromagnetic radiation having a dose of less than 10.0 mJ/cm2 and forming elements.

Abstract translation: 一种制造衬底的方法，包括将第一抗蚀剂涂覆在硬掩模上，将第一抗蚀剂的区域以10.0mJ / cm 2或更大的剂量暴露于电磁辐射，并去除所述和形成引导特征的一部分。 该方法还包括蚀刻硬掩模以在硬掩模中形成隔离特征，在形成硬掩模中的第二抗蚀剂的区域的隔离特征内施加第二抗蚀剂，以及将第二抗蚀剂的区域暴露于具有小于10.0的剂量的电磁辐射 mJ / cm 2和成形元件。

公开(公告)号：US20170263496A1

公开(公告)日：2017-09-14

申请号：US15529479

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MICHAEL J. LEESON ,  TODD R. YOUNKIN ,  EUNGNAK HAN ,  ROBERT L. BRISTOL

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/165 ,  H01L21/0271 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.