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公开(公告)号：US11416402B2
公开(公告)日：2022-08-16
申请号：US17068742
申请日：2020-10-12
申请人： Intel Corporation
发明人： Niranjan L. Cooray , Altug Koker , Vidhya Krishnan , Ronald W. Silvas , John H. Feit , Prasoonkumar Surti , Joydeep Ray , Abhishek R. Appu
IPC分类号： G06F12/0837 , G06F9/38 , G06F16/907 , H04L9/06 , G06F12/0811
摘要： Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.
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公开(公告)号：US10863138B2
公开(公告)日：2020-12-08
申请号：US15169262
申请日：2016-05-31
申请人： Intel Corporation
IPC分类号： H04N7/167 , H04L9/06 , H04N21/2347
摘要： Apparatuses, methods and storage medium associated with single pass parallel encryption are disclosed herein. In embodiments, an apparatus for computing may comprise an encryption engine to encrypt a video stream. The encryption engine may comprise a plurality of encryption pipelines to respectively encrypt a plurality of video sub-streams partitioned from the video stream in parallel in a single pass as the video sub-streams are being generated. The plurality of encryption pipelines may use a corresponding plurality of multi-part encryption counters to encrypt the corresponding video sub-streams as the video sub-streams are being generated. Each of the multi-part encryption counters used by one of the encryption pipelines may comprise a sub-portion that remains constant while encoding the corresponding video sub-stream, but the sub-key is unique for the one encryption pipeline, and differs from corresponding sub-portions of the multi-part encryption counters used by the other encryption pipelines. Other embodiments may be disclosed or claimed.
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公开(公告)号：US20230195519A1
公开(公告)日：2023-06-22
申请号：US17559352
申请日：2021-12-22
申请人： Intel Corporation
CPC分类号： G06F9/4893 , G06T1/20 , G06T1/60 , G06N20/00 , G06F1/3293 , G06F9/505
摘要： One embodiment provides an apparatus comprising a graphics processor device including a first compute engine and a second compute engine, wherein the second compute engine includes a subset of the functionality provided by the first compute engine and a lower power consumption relative to the first compute engine.
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公开(公告)号：US20230094002A1
公开(公告)日：2023-03-30
申请号：US17484711
申请日：2021-09-24
申请人： Intel Corporation
发明人： Hema Chand Nalluri , Jeffery S. Boles , Joseph Koston , Ankur N. Shah , Vidhya Krishnan , Vasanth Ranganathan , Joydeep Ray , Aditya Navale , Murali Ramadoss , James Valerio
摘要： Dynamic routing of texture-load in graphics processing is described. An example of an apparatus includes a graphics processor including a plurality of processing engines of a class of processing engines of the graphic processor; a set of queues for the plurality of processing engines; and a unified submit port for the plurality of processing engines, wherein the unified submit port is to notify a scheduler regarding availability of slots in the set of queues for receipt of workload contexts; and wherein, upon the unified submit port receiving a workload context for processing by the plurality of processing engines, the unified submit port is to detect an available processing engine of the plurality of processing engines and direct the received context to a slot of the set of queues for processing by the available processing engine.
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公开(公告)号：US10969999B2
公开(公告)日：2021-04-06
申请号：US16234655
申请日：2018-12-28
申请人： Intel Corporation
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/06 , G06F12/10 , G06F21/60 , G06F21/84 , G06F12/1045 , G06F12/084 , G06F21/83 , G06F12/0895 , G06F12/1036
摘要： An apparatus to facilitate a tracking of surface properties is disclosed. The apparatus includes one or more processors to receive a memory request, access a virtual to virtual page table to retrieve an address storing surface properties metadata, and process the memory request, wherein the virtual to virtual page table provides a mapping between a main surface and an auxiliary surface including the surface properties metadata.
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公开(公告)号：US20200288152A1
公开(公告)日：2020-09-10
申请号：US16647998
申请日：2017-12-05
申请人： INTEL CORPORATION
发明人： James Holland , Hiu-Fai Chan , Fangwen Fu , Qian Xu , Sang-Hee Lee , Vidhya Krishnan
IPC分类号： H04N19/182 , H04N19/423
摘要： A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.
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公开(公告)号：US20190296909A1
公开(公告)日：2019-09-26
申请号：US16435083
申请日：2019-06-07
申请人： Intel Corporation
摘要： An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US11018863B2
公开(公告)日：2021-05-25
申请号：US16435083
申请日：2019-06-07
申请人： Intel Corporation
摘要： An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号：US10599582B2
公开(公告)日：2020-03-24
申请号：US15276025
申请日：2016-09-26
申请人： Intel Corporation
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/1009 , G06F12/0802 , G06F12/1045 , G06F12/1036 , G06F12/10
摘要： A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.
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公开(公告)号：US10367639B2
公开(公告)日：2019-07-30
申请号：US15394324
申请日：2016-12-29
申请人： Intel Corporation
摘要： An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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