-
公开(公告)号:US20230094002A1
公开(公告)日:2023-03-30
申请号:US17484711
申请日:2021-09-24
申请人: Intel Corporation
发明人: Hema Chand Nalluri , Jeffery S. Boles , Joseph Koston , Ankur N. Shah , Vidhya Krishnan , Vasanth Ranganathan , Joydeep Ray , Aditya Navale , Murali Ramadoss , James Valerio
摘要: Dynamic routing of texture-load in graphics processing is described. An example of an apparatus includes a graphics processor including a plurality of processing engines of a class of processing engines of the graphic processor; a set of queues for the plurality of processing engines; and a unified submit port for the plurality of processing engines, wherein the unified submit port is to notify a scheduler regarding availability of slots in the set of queues for receipt of workload contexts; and wherein, upon the unified submit port receiving a workload context for processing by the plurality of processing engines, the unified submit port is to detect an available processing engine of the plurality of processing engines and direct the received context to a slot of the set of queues for processing by the available processing engine.
-
公开(公告)号:US20240095201A1
公开(公告)日:2024-03-21
申请号:US18459311
申请日:2023-08-31
申请人: Intel Corporation
发明人: David Puffer , Ankur Shah , Niranjan Cooray , Bryan White , Balaji Vembu , Hema Chand Nalluri , Kritika Bala
CPC分类号: G06F13/24 , G06F13/1668 , G06T1/20
摘要: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
-
公开(公告)号:US20220413704A1
公开(公告)日:2022-12-29
申请号:US17358914
申请日:2021-06-25
申请人: Intel Corporation
摘要: An apparatus to facilitate a dynamically scalable and partitioned copy engine is disclosed. The apparatus includes a processor comprising copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry to generate a plurality of surface data sub-blocks, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry.
-
公开(公告)号:US11288191B1
公开(公告)日:2022-03-29
申请号:US17132147
申请日:2020-12-23
申请人: Intel Corporation
发明人: Hema Chand Nalluri , Aditya Navale , Altug Koker , Brandon Fliflet , Jeffery S. Boles , James Valerio , Vasanth Ranganathan , Anirban Kundu , Pattabhiraman K
IPC分类号: G06F12/0802
摘要: An apparatus to facilitate memory flushing is disclosed. The apparatus comprises a cache memory, one or more processing resources, tracker hardware to dispatch workloads for execution at the processing resources and to monitor the workloads to track completion of the execution, range based flush (RBF) hardware to process RBF commands and generate a flush indication to flush data from the cache memory and a flush controller to receive the flush indication and perform a flush operation to discard data from the cache memory at an address range provided in the flush indication.
-
公开(公告)号:US11232531B2
公开(公告)日:2022-01-25
申请号:US15690201
申请日:2017-08-29
申请人: Intel Corporation
发明人: Hema Chand Nalluri , Balaji Vembu , Peter Doyle , Michael Apodaca
摘要: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.
-
公开(公告)号:US09489707B2
公开(公告)日:2016-11-08
申请号:US14039135
申请日:2013-09-27
申请人: INTEL CORPORATION
发明人: Hema Chand Nalluri , Joy Chandra , Prosun Chatterjee , Benjamin Pletcher , Yoav Harel , Steven Spangler
CPC分类号: G06T1/20 , G06F3/00 , G06F9/5083 , G06T2200/28
摘要: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
摘要翻译: 本文描述的实施例包括图形处理单元。 图形处理单元包括多个执行单元。 图形处理单元还包括多个采样器单元。 每个采样器单元对应于采样器调度逻辑单元和至少一个执行单元,并且采样器调度逻辑单元用于网络多个采样器单元。
-
公开(公告)号:US20240054595A1
公开(公告)日:2024-02-15
申请号:US17884755
申请日:2022-08-10
申请人: Intel Corporation
发明人: Joydeep Ray , Vasanth Ranganathan , James Valerio , Jeffery S. Boles , Hema Chand Nalluri , Aditya Navale , Ben J. Ashbaugh , Michal Mrozek , Murali Ramadoss , Hong Jiang , Ankur Shah
CPC分类号: G06T1/20 , G06T1/60 , G06F9/3855
摘要: Embodiments described herein provide a system of concurrent compute queues that enable the scheduling of a large number of compute contexts simultaneously on graphics processor hardware. One embodiment provides an apparatus comprising a system interface and a general-purpose graphics processor coupled with the system interface. The general-purpose graphics processor comprises a plurality of graphics processor hardware resources configured to be partitioned into a plurality of isolated partitions, each of the plurality of isolated partitions including a first command streamer, a second command streamer, and circuitry configured to schedule general-purpose graphics compute workloads submitted to a first plurality of command queues associated with the first command streamer and a second plurality of command queues associated with the second command streamer.
-
公开(公告)号:US11281837B2
公开(公告)日:2022-03-22
申请号:US15845788
申请日:2017-12-18
申请人: Intel Corporation
IPC分类号: G06F30/394 , G06F1/3234 , G06F13/40 , G06F30/30 , G06F30/398
摘要: In accordance with embodiments disclosed herein, there is provided systems and methods for router-based transaction routing for toggle reduction. An integrated circuit includes a transmitter circuit, receiver circuits, and a multicast bus coupled between the transmitter circuit and the receiver circuits. The multicast bus includes a first flow router circuit to route a multicast signal to a first receiver circuit of the plurality of receiver circuits and not route the multicast signal to a second receiver circuit of the plurality of receiver circuits.
-
公开(公告)号:US20220075746A1
公开(公告)日:2022-03-10
申请号:US17014023
申请日:2020-09-08
申请人: Intel Corporation
发明人: Hema Chand Nalluri , Ankur Shah , Joydeep Ray , Aditya Navale , Altug Koker , Murali Ramadoss , Niranjan L. Cooray , Jeffery S. Boles , Aravindh Anantaraman , David Puffer , James Valerio , Vasanth Ranganathan
IPC分类号: G06F13/40 , G06F13/16 , G06F9/30 , G06F9/52 , G06F12/0837 , G06F12/0888
摘要: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.
-
公开(公告)号:US10078879B2
公开(公告)日:2018-09-18
申请号:US14692984
申请日:2015-04-22
申请人: INTEL CORPORATION
发明人: Hema Chand Nalluri , Aditya Navale
CPC分类号: G06T1/20 , G06F9/48 , G06F9/52 , G06F15/167 , G09G5/001
摘要: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.
-
-
-
-
-
-
-
-
-