UNIFIED SUBMIT PORT FOR GRAPHICS PROCESSING

    公开(公告)号:US20230094002A1

    公开(公告)日:2023-03-30

    申请号:US17484711

    申请日:2021-09-24

    申请人: Intel Corporation

    IPC分类号: G06F9/48 G06T1/20

    摘要: Dynamic routing of texture-load in graphics processing is described. An example of an apparatus includes a graphics processor including a plurality of processing engines of a class of processing engines of the graphic processor; a set of queues for the plurality of processing engines; and a unified submit port for the plurality of processing engines, wherein the unified submit port is to notify a scheduler regarding availability of slots in the set of queues for receipt of workload contexts; and wherein, upon the unified submit port receiving a workload context for processing by the plurality of processing engines, the unified submit port is to detect an available processing engine of the plurality of processing engines and direct the received context to a slot of the set of queues for processing by the available processing engine.

    DYNAMICALLY SCALABLE AND PARTITIONED COPY ENGINE

    公开(公告)号:US20220413704A1

    公开(公告)日:2022-12-29

    申请号:US17358914

    申请日:2021-06-25

    申请人: Intel Corporation

    IPC分类号: G06F3/06 G06F9/38 G06F13/40

    摘要: An apparatus to facilitate a dynamically scalable and partitioned copy engine is disclosed. The apparatus includes a processor comprising copy engine hardware circuitry to facilitate copying surface data in memory and comprising: a plurality of copy front-end hardware circuitry to generate a plurality of surface data sub-blocks, wherein a number of the plurality of copy front-end hardware circuitry corresponds to a number of partitions configured for the processor, with each partition associated with a single copy front-end hardware circuitry; a plurality of copy back-end hardware circuitry to operate in parallel to process the plurality of surface data sub-blocks to perform memory accesses, wherein subsets of the plurality of copy back-end hardware circuitry are each associated with the single copy front-end hardware circuitry associated with each partition; and a connectivity matrix hardware circuitry to communicably connect the plurality of copy front-end hardware circuitry to the plurality of copy back-end hardware circuitry.

    Method and apparatus for efficient loop processing in a graphics hardware front end

    公开(公告)号:US11232531B2

    公开(公告)日:2022-01-25

    申请号:US15690201

    申请日:2017-08-29

    申请人: Intel Corporation

    IPC分类号: G06T1/20 G06T15/00

    摘要: Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.

    Process synchronization between engines using data in a memory location

    公开(公告)号:US10078879B2

    公开(公告)日:2018-09-18

    申请号:US14692984

    申请日:2015-04-22

    申请人: INTEL CORPORATION

    摘要: Memory-based semaphores are described that are useful for synchronizing processes between different processing engines. In one example, operations include executing a first process at a first processing engine, the executing including updating a memory register, sending a signal from the first processing engine to a second processing engine that the memory register has been updated, the signal including a memory register address to identify the updated memory register inline data and a dataword, fetching data from the memory register by the second processing engine, comparing the fetched data to the received dataword, and conditionally executing a next command of a second process at the second processing engine based on the comparison.