公开(公告)号：US10067829B2

公开(公告)日：2018-09-04

申请号：US14106571

申请日：2013-12-13

Applicant: INTEL CORPORATION

Inventor： Robert E. Frickey, III ,  Wei Fang ,  Ning Wu

IPC: G06F11/10 ,  G06F12/02

Abstract: Embodiments include apparatuses, method, and systems for organizing individual memory dice of a memory device into a plurality of virtual dice and designating one of the virtual dice of the memory device for storage of redundancy information. In one embodiment, a memory controller includes memory allocation logic to organize memory resources of individual memory dice of a memory device into a plurality of virtual dice, including a redundancy virtual die for storing redundancy information and a plurality of data virtual dice for storing data. The memory controller may further include input/output logic to write data to the data virtual dice of the non-volatile memory device, and redundancy information logic to generate redundancy information based on the data and to write the redundancy information to the redundancy virtual die of the non-volatile memory device.

公开(公告)号：US10679698B2

公开(公告)日：2020-06-09

申请号：US15939026

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Wei Fang ,  Albert Fazio

IPC: G11C11/00 ,  G11C13/00 ,  G06F13/40 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52 ,  G11C29/44 ,  G11C29/04

Abstract: A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

公开(公告)号：US20190103160A1

公开(公告)日：2019-04-04

申请号：US15721438

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Prashant S. Damle ,  Nevil N. Gajera

IPC: G11C13/00

Abstract: In one embodiment, an apparatus comprises a first memory array comprising a plurality of phase change memory (PCM) cells; and a controller to track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and adjust, based on the first cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the first memory array.

公开(公告)号：US10777271B2

公开(公告)日：2020-09-15

申请号：US15721438

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Prashant S. Damle ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C13/00 ,  G11C29/02

Abstract: In one embodiment, an apparatus comprises a first memory array comprising a plurality of phase change memory (PCM) cells; and a controller to track a first cycle count metric based at least in part on a number of writes performed to at least a portion of the first memory array; and adjust, based on the first cycle count metric, a demarcation voltage to be applied during read operations performed on PCM cells of the first memory array.

公开(公告)号：US10331345B2

公开(公告)日：2019-06-25

申请号：US15721394

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Kiran Pangal ,  Prashant S. Damle

IPC: G11C16/28 ,  G06F3/06 ,  G06F13/16 ,  G06F11/10 ,  G06F12/02

Abstract: In one embodiment, an apparatus comprises a memory array comprising a plurality of phase change memory (PCM) cells; and a controller to determine to read data stored by the plurality of PCM cells independent of a read command from a host device; and in response to the determination to read data stored by the plurality of PCM cells independent of a read command from a host device, perform a dummy read operation on the plurality of PCM cells and perform an additional read operation on the plurality of PCM cells.

公开(公告)号：US20190102088A1

公开(公告)日：2019-04-04

申请号：US15721394

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wei Fang ,  Kiran Pangal ,  Prashant S. Damle

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/16 ,  G06F11/10

CPC classification number: G06F3/0602 ,  G06F3/0653 ,  G06F3/0683 ,  G06F11/1044 ,  G06F12/0246 ,  G06F13/1668 ,  G06F2003/0697

Abstract: In one embodiment, an apparatus comprises a memory array comprising a plurality of phase change memory (PCM) cells; and a controller to determine to read data stored by the plurality of PCM cells independent of a read command from a host device; and in response to the determination to read data stored by the plurality of PCM cells independent of a read command from a host device, perform a dummy read operation on the plurality of PCM cells and perform an additional read operation on the plurality of PCM cells.